[Mesa-dev] [PATCH 3/3] radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits

[Marek Olšák]

On Sat, Mar 19, 2016 at 4:37 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> This fixes arb_shader_image_load_store-host-mem-barrier.
> ---
>  src/gallium/drivers/radeonsi/si_state.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 6dcd532..4093921 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3535,7 +3535,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
>         if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
>                      PIPE_BARRIER_SHADER_BUFFER |
>                      PIPE_BARRIER_TEXTURE |
> -                    PIPE_BARRIER_IMAGE)) {
> +                    PIPE_BARRIER_IMAGE |
> +                    PIPE_BARRIER_INDEX_BUFFER |
> +                    PIPE_BARRIER_STREAMOUT_BUFFER)) {

The hw reads the index buffer via TC L2 on VI only. The index buffer
is uncached on older chips.

I think this patch needs to flush TC L2 for PIPE_BARRIER_INDEX_BUFFER
if the chip family is not VI.

Patches 1-2:
Reviewed-by: Marek Olšák <marek.olsak at amd.com>


Marek