[Mesa-dev] [PATCH 23/59] i965/fs: use the NIR bit size when creating registers

[Samuel Iglesias Gonsálvez]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256



On 30/04/16 09:26, Kenneth Graunke wrote:
> On Friday, April 29, 2016 1:29:20 PM PDT Samuel Iglesias Gonsálvez
> wrote:
>> From: Connor Abbott <connor.w.abbott at intel.com>
>> 
>> v2 (Iago): - Squashed bits from 'support double precission
>> constant operands for the implementation of 64-bit
>> emit_load_const'. - Do not use BRW_REGISTER_TYPE_D for all 32-bit
>> registers since that
> breaks
>> asserts and functionality for some piglit tests. Just keep 32-bit
>> types untouched and add 64-bit support. - Use DF instead of Q for
>> 64-bit registers. Otherwise the code we generate will use Q
>> sometimes and DF others and we hit unwanted DF/Q conversions, so
>> always use DF.
>> 
>> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com> 
>> Signed-off-by: Tapani Palli <tapani.palli at intel.com> 
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> 
>> Signed-off-by: Iago Toral Quiroga <itoral at igalia.com> --- 
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
>> +++++++++++++++++++++++
> +--------
>> 1 file changed, 25 insertions(+), 8 deletions(-)
>> 
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
>> b/src/mesa/drivers/
> dri/i965/brw_fs_nir.cpp
>> index 360e2c9..333ca2b 100644 ---
>> a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++
>> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -365,7 +365,9 @@
>> fs_visitor::nir_emit_impl(nir_function_impl *impl) unsigned
>> array_elems = reg->num_array_elems == 0 ? 1 :
>> reg->num_array_elems; unsigned size = array_elems *
>> reg->num_components; -      nir_locals[reg->index] =
>> bld.vgrf(BRW_REGISTER_TYPE_F, size); +      brw_reg_type reg_type
>> = +         reg->bit_size == 32 ? BRW_REGISTER_TYPE_F :
>> BRW_REGISTER_TYPE_DF; +      nir_locals[reg->index] =
>> bld.vgrf(reg_type, size); }
>> 
>> nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg, @@
>> -1201,10 +1203,21 @@ void fs_visitor::nir_emit_load_const(const
>> fs_builder &bld, nir_load_const_instr *instr) { -   fs_reg reg =
>> bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components); +
>> brw_reg_type reg_type = +      instr->def.bit_size == 32 ?
>> BRW_REGISTER_TYPE_D :
> BRW_REGISTER_TYPE_DF;
>> +   fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
>> 
>> -   for (unsigned i = 0; i < instr->def.num_components; i++) -
>> bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i])); +
>> switch (instr->def.bit_size) { +   case 32: +      for (unsigned
>> i = 0; i < instr->def.num_components; i++) +
>> bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i])); +
>> break; + +   case 64: +      for (unsigned i = 0; i <
>> instr->def.num_components; i++) +         bld.MOV(offset(reg,
>> bld, i), brw_imm_df(instr->value.f64[i])); +      break;
> 
> How about adding:
> 
> default: unreachable("Invalid bit size")
> 
> Either way is fine.
> 

I will add it.

Thanks,

Sam

>> +   }
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2

iQIcBAEBCAAGBQJXKD8+AAoJEH/0ujLxfcNDIp8QAKZJYf1bMytK+NJ2YPGq4CCB
+O2OHApYHlvflDQzG5x0dMc70EANaiytQF6JF+uH1gcXWEewNz5J8FPK9SqG2OFO
qN78vhndCNUVuNlAI+fb9kOLic6IkS6ZR6vl6AWvcnwyefCyCkpY26QCjCFtvmzN
Al0L0RkQbvFQaHEHyXFmBqCwlq+hISPMzsSZUZg9hON5273wLHEyCVq3qyaR4P5w
QX54Bb10CYbQ0hzr9oopzeEMuxVdgTH88vIoO2IpDDvZmcOHpt53yizpSivKhIuo
hjK3eAoJpMTPWM63OGgePwVQV6FdaIjgAZzRavR9iJ4ceJfGYVSb1iGYm3z4dbCI
w4SczhO5yLE3DQtsGOzlmHfFmZKefXcOMCjBWLJ+eLMLS9SmoQb3qdw9iodr1YTC
kenkUQUgtmQCan0Rm4UtjlOUUp1uo3g1ezH9rXLe7FquC1oUYev7SajJQGCKlRg1
TLii6nCx9S4oN+NRimkqO1CznN7X9ulJmI7JH/cJ7YCzrOg17dOrzm61ovyo5Hes
5y38+Qhd6H+WYy8kEBjKUqx2zr5UFiaxP1F18Q9/tT4szThjUs1HyNrFN4Yvp1R2
pWFbOqyy7b/aX0OXjLmN1sjVN74+sBfwgzCKos/3V/wqe3ylE7FKGJPaiOFLJ9di
dDxSOfvJVwWX7jj/VVR6
=1Q1f
-----END PGP SIGNATURE-----