[Mesa-dev] [PATCH] Revert "i965: Always use Y-tiled buffers on SKL+"

Hans de Goede hdegoede at redhat.com
Sun May 8 09:35:24 UTC 2016


This reverts commit 6a0d036483caf87d43ebe2edd1905873446c9589.

This commit breaks both gdm on wayland as well as gnome-shell on Xorg
(with the modesetting driver) on my skylake desktop with 2 hdmi attached
1920x1080 dvi-monitors.

The symptons in both cases are both monitors showing whatever was there
before with a mouse cursor drawn centered on the primary monitor. In the
gnome-shell on Xorg case I can still vt-switch and after vt-switching
back Xorg exits with an error.

When this commit is not reverted the following errors show up in Xorg.log
when starting X with gnome-shell: "failed to add fb -22", this error
also triggers the exit with an error on vt-switching back.

These errors come from the modesetting driver:

    if (drmmode->fb_id == 0) {
        ret = drmModeAddFB(drmmode->fd,
                           pScrn->virtualX, height,
                           pScrn->depth, pScrn->bitsPerPixel,
                           drmmode_bo_get_pitch(&drmmode->front_bo),
                           drmmode_bo_get_handle(&drmmode->front_bo),
                           &drmmode->fb_id);
        if (ret < 0) {
            ErrorF("failed to add fb %d\n", ret);
            return FALSE;
        }
    }

Signed-off-by: Hans de Goede <hdegoede at redhat.com>
---
 src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |  4 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c   | 10 ++--------
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h   |  3 +--
 src/mesa/drivers/dri/i965/intel_screen.c        | 21 +++------------------
 4 files changed, 8 insertions(+), 30 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 7760cce..76988bf 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -244,7 +244,7 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
        * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
        * with X alignment multiplied by 16 and Y alignment multiplied by 32.
        */
-      intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align);
+      intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
       x_align *= 16;
 
       /* SKL+ line alignment requirement for Y-tiled are half those of the prior
@@ -838,7 +838,7 @@ brw_get_resolve_rect(const struct brw_context *brw,
     * by a factor of 2.
     */
 
-   intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align);
+   intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
    if (brw->gen >= 9) {
       x_scaledown = x_align * 8;
       y_scaledown = y_align * 8;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3d8f48e..94f6333 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -144,8 +144,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
  *   by half the block width, and Y coordinates by half the block height.
  */
 void
-intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
-                                 const struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
                                  unsigned *width_px, unsigned *height)
 {
    switch (mt->tiling) {
@@ -157,11 +156,6 @@ intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
       *height = 4;
       break;
    case I915_TILING_X:
-      /* The docs are somewhat confusing with the way the tables are displayed.
-       * However, it does clearly state: "MCS and Lossless compression is
-       * supported for TiledY/TileYs/TileYf non-MSRTs only."
-       */
-      assert(brw->gen < 9);
       *width_px = 64 / mt->cpp;
       *height = 2;
    }
@@ -1558,7 +1552,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
    const mesa_format format = MESA_FORMAT_R_UINT32;
    unsigned block_width_px;
    unsigned block_height;
-   intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height);
+   intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height);
    unsigned width_divisor = block_width_px * 4;
    unsigned height_divisor = block_height * 8;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 21e4718..7862152 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -663,8 +663,7 @@ struct intel_mipmap_tree
 };
 
 void
-intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
-                                 const struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
                                  unsigned *width_px, unsigned *height);
 
 bool
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 878901a..db9d94d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -516,11 +516,7 @@ intel_create_image(__DRIscreen *screen,
    int cpp;
    unsigned long pitch;
 
-   if (intelScreen->devinfo->gen >= 9) {
-      tiling = I915_TILING_Y;
-   } else {
-      tiling = I915_TILING_X;
-   }
+   tiling = I915_TILING_X;
    if (use & __DRI_IMAGE_USE_CURSOR) {
       if (width != 64 || height != 64)
 	 return NULL;
@@ -1148,14 +1144,8 @@ intel_detect_swizzling(struct intel_screen *screen)
    drm_intel_bo *buffer;
    unsigned long flags = 0;
    unsigned long aligned_pitch;
+   uint32_t tiling = I915_TILING_X;
    uint32_t swizzle_mode = 0;
-   uint32_t tiling;
-
-   if (screen->devinfo->gen >= 9) {
-      tiling = I915_TILING_Y;
-   } else {
-      tiling = I915_TILING_X;
-   }
 
    buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test",
 				     64, 64, 4,
@@ -1581,12 +1571,7 @@ intelAllocateBuffer(__DRIscreen *screen,
       return NULL;
 
    /* The front and back buffers are color buffers, which are X tiled. */
-   uint32_t tiling;
-   if (intelScreen->devinfo->gen >= 9) {
-      tiling = I915_TILING_Y;
-   } else {
-      tiling = I915_TILING_X;
-   }
+   uint32_t tiling = I915_TILING_X;
    unsigned long pitch;
    int cpp = format / 8;
    intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr,
-- 
2.7.4



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