[Mesa-dev] [PATCH 4/4] gallium/radeon: align alignments for better buffer reuse

[Michel Dänzer]

On 09.05.2016 17:02, Bas Nieuwenhuizen wrote:
> On Mon, May 9, 2016 at 5:59 AM, Michel Dänzer <michel at daenzer.net> wrote:
>> On 08.05.2016 21:21, Marek Olšák wrote:
>>> From: Marek Olšák <marek.olsak at amd.com>
>>>
>>> ---
>>>  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c     | 1 +
>>>  src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 1 +
>>>  2 files changed, 2 insertions(+)
>>>
>>> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> index eb28ba9..ed12f30 100644
>>> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> @@ -470,6 +470,7 @@ amdgpu_bo_create(struct radeon_winsys *rws,
>>>      * like constant/uniform buffers, can benefit from better and more reuse.
>>>      */
>>>     size = align64(size, ws->info.gart_page_size);
>>> +   alignment = align(alignment, ws->info.gart_page_size);
>>>
>>>     /* Only set one usage bit each for domains and flags, or the cache manager
>>>      * might consider different sets of domains / flags compatible
>>> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>>> index b24964f..b07afe6 100644
>>> --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>>> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>>> @@ -732,6 +732,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
>>>       * like constant/uniform buffers, can benefit from better and more reuse.
>>>       */
>>>      size = align(size, ws->info.gart_page_size);
>>> +    alignment = align(alignment, ws->info.gart_page_size);
>>>
>>>      /* Only set one usage bit each for domains and flags, or the cache manager
>>>       * might consider different sets of domains / flags compatible
>>>
>>
>> This is superfluous: ws->info.gart_page_size is the CPU page size. TTM
>> only tracks BOs at CPU page size granularity, so all BOs implicitly have
>> this alignment. For GPUVM, since we're aligning the BO size, all VM
>> address spaces we assign are implicitly aligned as well.
> 
> That alignment does get used by the buffer cache though, which does
> not implicitly align on page sizes. The buffer cache only gives
> buffers that have the exact same alignment as the request and with
> this patch the number of different alignments that can be used in the
> buffer cache is reduced.

I see. Maybe something along those lines can be added to the commit log,
but either way this patch is

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>

as well.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer