[Mesa-dev] [PATCH 1/2] i965: Actually assign binding table offsets for the TCS.

[Kristian Høgsberg Kristensen]

Kenneth Graunke <kenneth at whitecape.org> writes:

> As far as I can tell, this was just entirely missing...honestly, I'm
> not sure how anything worked at all.
>
> Caught by noticing GPU hangs in image load store tests with scalar TCS,
> but probably has broader implications.

Yeah, presumably not a lot of TCSs use textures or buffers, they just
have to determine the tessellation level... who knows.

Both patches

Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>

> Cc: mesa-stable at lists.freedesktop.org
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_tcs.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
> index 98ed2b2..e8178c6 100644
> --- a/src/mesa/drivers/dri/i965/brw_tcs.c
> +++ b/src/mesa/drivers/dri/i965/brw_tcs.c
> @@ -168,6 +168,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,
>  {
>     struct gl_context *ctx = &brw->ctx;
>     const struct brw_compiler *compiler = brw->intelScreen->compiler;
> +   const struct brw_device_info *devinfo = compiler->devinfo;
>     struct brw_stage_state *stage_state = &brw->tcs.base;
>     nir_shader *nir;
>     struct brw_tcs_prog_data prog_data;
> @@ -209,6 +210,10 @@ brw_codegen_tcs_prog(struct brw_context *brw,
>     prog_data.base.base.nr_params = param_count;
>  
>     if (tcs) {
> +      brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo,
> +                                              shader_prog, &tcp->program.Base,
> +                                              &prog_data.base.base, 0);
> +
>        prog_data.base.base.image_param =
>           rzalloc_array(NULL, struct brw_image_param, tcs->NumImages);
>        prog_data.base.base.nr_image_params = tcs->NumImages;
> -- 
> 2.8.2
>
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