[Mesa-dev] [PATCH 10/15] i965: take care of doubles when lowering VS inputs

[Kenneth Graunke]

On Thursday, April 28, 2016 1:40:40 PM PDT Antia Puentes wrote:
> From: "Juan A. Suarez Romero" <jasuarez at igalia.com>
> 
> Input attributes can require 2 vec4 or 1 vec4 depending on whether they
> are double-precision or not.
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp   | 13 +++++++++++++
>  src/mesa/drivers/dri/i965/brw_nir.c    |  3 ++-
>  src/mesa/drivers/dri/i965/brw_shader.h |  1 +
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/
i965/brw_fs.cpp
> index 5e20ef9..4b8835d 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -645,6 +645,19 @@ type_size_vec4_times_4(const struct glsl_type *type)
>     return 4 * type_size_vec4(type);
>  }
>  
> +/* Attribute arrays are loaded as one vec4 per element (or matrix column),
> + * except for double-precision types, which are loaded as one dvec4.
> + */
> +extern "C" int
> +type_size_vs_input(const struct glsl_type *type)
> +{
> +   if (type->is_double()) {
> +      return type_size_vec4(type) / 2;
> +   } else {
> +      return type_size_vec4(type);
> +   }
> +}

Hmm, this is right, but it confused me at first.  At this point, we do
nir_lower_io on VERT_ATTRIB_* values, which count doubles as one slot.
When we remap, we fix it up to actual offsets that properly account for
doubles taking up extra space.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

> +
>  /**
>   * Create a MOV to read the timestamp register.
>   *
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/
i965/brw_nir.c
> index 1d14437..8b7cd8e 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> @@ -23,6 +23,7 @@
>  
>  #include "brw_nir.h"
>  #include "brw_shader.h"
> +#include "compiler/glsl_types.h"
>  #include "compiler/nir/glsl_to_nir.h"
>  #include "compiler/nir/nir_builder.h"
>  #include "program/prog_to_nir.h"
> @@ -220,7 +221,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>      * loaded as one vec4 or dvec4 per element (or matrix column), depending 
on
>      * whether it is a double-precision type or not.
>      */
> -   nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
> +   nir_lower_io(nir, nir_var_shader_in, type_size_vs_input);
>  
>     /* This pass needs actual constants */
>     nir_opt_constant_folding(nir);
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/
i965/brw_shader.h
> index f6f6167..8af058b 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -292,6 +292,7 @@ struct gl_shader *brw_new_shader(struct gl_context *ctx, 
GLuint name, GLuint typ
>  int type_size_scalar(const struct glsl_type *type);
>  int type_size_vec4(const struct glsl_type *type);
>  int type_size_vec4_times_4(const struct glsl_type *type);
> +int type_size_vs_input(const struct glsl_type *type);
>  
>  unsigned tesslevel_outer_components(GLenum tes_primitive_mode);
>  unsigned tesslevel_inner_components(GLenum tes_primitive_mode);
> 

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