[Mesa-dev] [PATCH 05/15] i965/fs: shuffle 32bits into 64bits for doubles

[Juan A. Suarez Romero]

On Tue, 2016-05-10 at 00:15 -0700, Kenneth Graunke wrote:
> On Thursday, April 28, 2016 1:40:35 PM PDT Antia Puentes wrote:
> > 
> > From: "Juan A. Suarez Romero" <jasuarez at igalia.com>
> > 
> > VS Thread Payload handles attributes in URB as vec4, no matter if
> > they
> > are actually single or double precision.
> > 
> > So with double-precision types, value ends up in the registers
> > split in
> > 32bits chunks, in different positions.
> > 
> > We need to shuffle the chunks to get the doubles correctly.
> Are you saying that it shows up as
> 
>     high0 high1 high2 high3 low0 low1 low2 low3
> 
> rather than
> 
>     high0 low0 high1 low1 high2 low2 high3 low3
> 
> ...?  That's kind of strange...
> 


Correct.

Well, it is not so strange when you figure out how it is working. So
yeah, answering your next question, I have to figure it out.

> Is this documented somewhere, or did you just have to figure it out?
> I see things saying "up to 4 32-bit values", but not much explanation
> about what happens with R64.*PASSTHRU...
> 

R64*PASSTHRU* only affects when copying data from the buffers to the
URB. Roughly speaking can be seen as 2 R32*PASSTHRU* executions.

But it says nothing about how to push content from URB to registers.
This is done through the VS Thread Payload, and it deals with 32 bit
content.

Let's show an example. For simplicity, I'll use a dvec2, former by two
values: d0 and d1.

We use R64*PASSTHRU* to upload the value. So in the URB you have (d0,
d1), each one 64bits value.

But the VS Thread Payload will not see it as 64 bits elements, but as
32 bits elements. So it sees something like (high0, low0, high1, low1).

In SIMD8 VS Thread Payload documentation, it explains how vertex data
is pushed inside. From there I got the idea content was read as (high0,
high1, low0, low1).

Also, a couple of tests I was doing was just giving a clue that the
content was being pushed shuffled.


	J.A.