[Mesa-dev] [PATCH 05/15] i965/fs: shuffle 32bits into 64bits for doubles

[Juan A. Suarez Romero]

On Tue, 2016-05-10 at 13:18 -0700, Kenneth Graunke wrote:
> On Thursday, April 28, 2016 1:40:35 PM PDT Antia Puentes wrote:
> > From: "Juan A. Suarez Romero" <jasuarez at igalia.com>
> > 
> > VS Thread Payload handles attributes in URB as vec4, no matter if
> they
> > are actually single or double precision.
> > 
> > So with double-precision types, value ends up in the registers
> split in
> > 32bits chunks, in different positions.
> > 
> > We need to shuffle the chunks to get the doubles correctly.
> > ---
> >  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/
> dri/i965/brw_fs_nir.cpp
> > index 0ff3eaf..4362308 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > @@ -3173,6 +3173,12 @@ fs_visitor::nir_emit_intrinsic(const
> fs_builder &bld, 
> nir_intrinsic_instr *instr
> >        for (unsigned j = 0; j < instr->num_components; j++) {
> >           bld.MOV(offset(dest, bld, j), offset(src, bld, j));
> >        }
> > +      if (type_sz(src.type) == 8)
> > +         SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA(bld,
> > +                                                 offset(dest, bld,
> 0),
> > +                                                 offset(dest, bld,
> 0),
> 
> Isn't this just dest, dest then? :)


Good catch! :D

	J.A.
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