[Mesa-dev] [PATCH] Integrate precise trig into configuration infrastructure

[Eero Tamminen]

Hi,

The known cases where this workaround caused slowdown were fixed,  so 
why not just unconditionally enable it?

Or is there still some case where workaround causes a measurable slowdown?


	- Eero

On 11.05.2016 23:32, Gurchetan Singh wrote:
> With this change, to enable precise SIN and COS instructions
> on Intel hardware, one can put
>
> <option name="precise_trig" value="true"/>
>
> in the proper drirc file.
>
> V2: Make option name more generic
> ---
>   src/mesa/drivers/dri/common/xmlpool/t_options.h | 5 +++++
>   src/mesa/drivers/dri/i965/brw_compiler.c        | 2 --
>   src/mesa/drivers/dri/i965/brw_context.c         | 3 +++
>   src/mesa/drivers/dri/i965/intel_screen.c        | 2 ++
>   4 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/common/xmlpool/t_options.h b/src/mesa/drivers/dri/common/xmlpool/t_options.h
> index e5cbc46..4b298a4 100644
> --- a/src/mesa/drivers/dri/common/xmlpool/t_options.h
> +++ b/src/mesa/drivers/dri/common/xmlpool/t_options.h
> @@ -158,6 +158,11 @@ DRI_CONF_OPT_BEGIN_B(force_s3tc_enable, def) \
>           DRI_CONF_DESC(en,gettext("Enable S3TC texture compression even if software support is not available")) \
>   DRI_CONF_OPT_END
>
> +#define DRI_CONF_PRECISE_TRIG(def) \
> +DRI_CONF_OPT_BEGIN_B(precise_trig, def) \
> +        DRI_CONF_DESC(en,gettext("Prefer accuracy over performance in trig functions")) \
> +DRI_CONF_OPT_END
> +
>   #define DRI_CONF_COLOR_REDUCTION_ROUND 0
>   #define DRI_CONF_COLOR_REDUCTION_DITHER 1
>   #define DRI_CONF_COLOR_REDUCTION(def) \
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c b/src/mesa/drivers/dri/i965/brw_compiler.c
> index 7c1b7e4..9ef7357 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.c
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.c
> @@ -145,8 +145,6 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
>      brw_fs_alloc_reg_sets(compiler);
>      brw_vec4_alloc_reg_set(compiler);
>
> -   compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
> -
>      compiler->scalar_stage[MESA_SHADER_VERTEX] =
>         devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
>      compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 26514a0..160f232 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -776,6 +776,9 @@ brw_process_driconf_options(struct brw_context *brw)
>
>      brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile");
>
> +   brw->intelScreen->compiler->precise_trig =
> +      driQueryOptionb(&brw->optionCache, "precise_trig");
> +
>      ctx->Const.ForceGLSLExtensionsWarn =
>         driQueryOptionb(options, "force_glsl_extensions_warn");
>
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
> index f9b5484..af8c4f4 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -65,6 +65,8 @@ DRI_CONF_BEGIN
>      DRI_CONF_SECTION_QUALITY
>         DRI_CONF_FORCE_S3TC_ENABLE("false")
>
> +      DRI_CONF_PRECISE_TRIG("false")
> +
>         DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
>                 DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the "
>                               "given integer. If negative, then do not clamp.")
>