[Mesa-dev] [PATCH 2/3] i965: Support instanced GS inputs in the scalar backend.

[Kenneth Graunke]

On Thursday, May 12, 2016 12:19:16 AM PDT Jordan Justen wrote:
> On 2016-05-09 15:36:42, Kenneth Graunke wrote:
> > Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> > ---
> >  src/mesa/drivers/dri/i965/brw_fs_nir.cpp          | 39 ++++++++++++++++++
+++--
> >  src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |  3 --
> >  2 files changed, 36 insertions(+), 6 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/
dri/i965/brw_fs_nir.cpp
> > index 9fd048a..33e4097 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > @@ -1761,7 +1761,9 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
> >      */
> >     const bool is_point_size = (base_offset == 0);
> >  
> > -   if (offset_const != NULL && vertex_const != NULL &&
> > +   /* TODO: figure out push input layout for invocations == 1 */
> > +   if (gs_prog_data->invocations == 1 &&
> > +       offset_const != NULL && vertex_const != NULL &&
> >         4 * (base_offset + offset_const->u32[0]) < push_reg_count) {
> >        int imm_offset = (base_offset + offset_const->u32[0]) * 4 +
> >                         vertex_const->u32[0] * push_reg_count;
> > @@ -1783,7 +1785,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
> >     gs_prog_data->base.include_vue_handles = true;
> >  
> >     unsigned first_icp_handle = gs_prog_data->include_primitive_id ? 3 : 
2;
> > -   fs_reg icp_handle;
> > +   fs_reg icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
> >  
> >     if (gs_prog_data->invocations == 1) {
> >        if (vertex_const) {
> > @@ -1807,7 +1809,6 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
> >           fs_reg channel_offsets = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
> >           fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
> >           fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
> > -         icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
> >  
> >           /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
> >           bld.MOV(sequence, fs_reg(brw_imm_v(0x76543210)));
> > @@ -1828,6 +1829,38 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
> >                    fs_reg(icp_offset_bytes),
> >                    brw_imm_ud(nir->info.gs.vertices_in * REG_SIZE));
> >        }
> > +   } else {
> > +      assert(gs_prog_data->invocations > 1);
> > +
> > +      if (vertex_const) {
> > +         assert(devinfo->gen >= 9 || vertex_const->i32[0] <= 5);
> > +         bld.MOV(icp_handle,
> > +                 retype(brw_vec1_grf(first_icp_handle +
> > +                                     vertex_const->i32[0] / 8,
> > +                                     vertex_const->i32[0] % 8),
> > +                        BRW_REGISTER_TYPE_UD));
> > +      } else {
> > +         /* The vertex index is non-constant.  We need to use indirect
> > +          * addressing to fetch the proper URB handle.
> > +          *
> 
> Extra comment line
> 
> > +          */
> > +         fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
> > +
> > +         /* Convert vertex_index to bytes (multiply by 4) */
> > +         bld.SHL(icp_offset_bytes,
> > +                 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
> > +                 brw_imm_ud(2u));
> > +
> > +         /* Use first_icp_handle as the base offset.  There is one 
register
> > +          * of URB handles per vertex, so inform the register allocator 
that
> > +          * we might read up to nir->info.gs.vertices_in registers.
> 
> I guess with the div round up, this comment is a bit off?
> 

Oh, good catch!  I've changed it to:

 /* Use first_icp_handle as the base offset.  There is one DWord 
  * of URB handles per vertex, so inform the register allocator that
  * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
  */

> For the both the 3+2 series,
> 
> Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

Thank you!
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