[Mesa-dev] [PATCH 2/5] anv: Keep track of whether the data cache should be enabled in L3

[Jason Ekstrand]

On Wed, May 11, 2016 at 4:22 PM, Jordan Justen <jordan.l.justen at intel.com>
wrote:

> If images or shader buffers are used, we will enable the data cache in
> the the L3 config.
>
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> ---
>  src/intel/vulkan/anv_pipeline.c  | 8 +++++++-
>  src/intel/vulkan/anv_private.h   | 1 +
>  src/intel/vulkan/genX_pipeline.c | 2 ++
>  3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/anv_pipeline.c
> b/src/intel/vulkan/anv_pipeline.c
> index 5800e68..fcaa450 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -331,8 +331,12 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
>     if (pipeline->layout &&
> pipeline->layout->stage[stage].has_dynamic_offsets)
>        prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
>
> -   if (nir->info.num_images > 0)
> +   if (nir->info.num_images > 0) {
>        prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
> +      pipeline->needs_data_cache |= true;
>

This can just be "= true"


> +   }
> +
> +   pipeline->needs_data_cache |= nir->info.num_ssbos > 0;
>

Maybe use "if (nir->info.num_ssbos >= 0)" to make it look more like the one
above?


>
>     if (prog_data->nr_params > 0) {
>        /* XXX: I think we're leaking this */
> @@ -1138,6 +1142,8 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
>
>     pipeline->use_repclear = extra && extra->use_repclear;
>
> +   pipeline->needs_data_cache = false;
> +
>     /* When we free the pipeline, we detect stages based on the NULL status
>      * of various prog_data pointers.  Make them NULL by default.
>      */
> diff --git a/src/intel/vulkan/anv_private.h
> b/src/intel/vulkan/anv_private.h
> index d8a2194..fb308eb 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -1403,6 +1403,7 @@ struct anv_pipeline {
>     struct anv_pipeline_bind_map
>  bindings[MESA_SHADER_STAGES];
>
>     bool                                         use_repclear;
> +   bool                                         needs_data_cache;
>
>     const struct brw_stage_prog_data *
>  prog_data[MESA_SHADER_STAGES];
>     uint32_t
>  scratch_start[MESA_SHADER_STAGES];
> diff --git a/src/intel/vulkan/genX_pipeline.c
> b/src/intel/vulkan/genX_pipeline.c
> index 2328920..2a41b2d 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -74,6 +74,8 @@ genX(compute_pipeline_create)(
>     pipeline->active_stages = 0;
>     pipeline->total_scratch = 0;
>
> +   pipeline->needs_data_cache = false;
> +
>     assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
>     ANV_FROM_HANDLE(anv_shader_module, module,  pCreateInfo->stage.module);
>     anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
> --
> 2.8.1
>
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>
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