[Mesa-dev] [PATCH 1/2] i965: Move compression control decisions into a helper function.

[Kenneth Graunke]

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: currojerez at riseup.net
---
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 61 ++++++++++++++------------
 1 file changed, 34 insertions(+), 27 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index b9000d6..824d0d0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1692,6 +1692,38 @@ fs_generator::enable_debug(const char *shader_name)
    this->shader_name = shader_name;
 }
 
+static enum brw_compression
+compression_for_inst(const fs_inst *inst)
+{
+   switch (inst->exec_size) {
+   case 1:
+   case 2:
+   case 4:
+      assert(inst->force_writemask_all);
+      return BRW_COMPRESSION_NONE;
+      break;
+   case 8:
+      if (inst->force_sechalf) {
+         return BRW_COMPRESSION_2NDHALF;
+      } else {
+         return BRW_COMPRESSION_NONE;
+      }
+      break;
+   case 16:
+   case 32:
+      /* If the instruction writes to more than one register, it needs to
+       * be a "compressed" instruction on Gen <= 5.
+       */
+      if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
+         return BRW_COMPRESSION_COMPRESSED;
+      else
+         return BRW_COMPRESSION_NONE;
+      break;
+   default:
+      unreachable("Invalid instruction width");
+   }
+}
+
 int
 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
 {
@@ -1736,33 +1768,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
       if (unlikely(debug_flag))
          annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
 
-      switch (inst->exec_size) {
-      case 1:
-      case 2:
-      case 4:
-         assert(inst->force_writemask_all);
-         brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
-         break;
-      case 8:
-         if (inst->force_sechalf) {
-            brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
-         } else {
-            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
-         }
-         break;
-      case 16:
-      case 32:
-         /* If the instruction writes to more than one register, it needs to
-          * be a "compressed" instruction on Gen <= 5.
-          */
-         if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
-            brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
-         else
-            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
-         break;
-      default:
-         unreachable("Invalid instruction width");
-      }
+      enum brw_compression compression = compression_for_inst(inst);
+      brw_set_default_compression_control(p, compression);
 
       for (unsigned int i = 0; i < inst->sources; i++) {
 	 src[i] = brw_reg_from_fs_reg(p, inst, &inst->src[i], devinfo->gen);
-- 
2.8.2