[Mesa-dev] [PATCH 04/14] i965/blorp: Use prog data counters to guide sf/sbe setup
Topi Pohjolainen
topi.pohjolainen at intel.com
Wed May 25 16:08:39 UTC 2016
just as core upload logic does.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 3 ++-
src/mesa/drivers/dri/i965/brw_blorp.h | 8 +++++++-
src/mesa/drivers/dri/i965/gen6_blorp.c | 10 ++++++++--
src/mesa/drivers/dri/i965/gen7_blorp.c | 10 ++++++++--
src/mesa/drivers/dri/i965/gen8_blorp.c | 15 ++++++++++++---
5 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9590968..ce37838 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -142,7 +142,6 @@ brw_blorp_params_init(struct brw_blorp_params *params)
memset(params, 0, sizeof(*params));
params->hiz_op = GEN6_HIZ_OP_NONE;
params->fast_clear_op = 0;
- params->num_varyings = 0;
params->num_draw_buffers = 1;
params->num_layers = 1;
}
@@ -232,6 +231,8 @@ brw_blorp_compile_nir_shader(struct brw_context *brw, struct nir_shader *nir,
prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2;
prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2;
prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch;
+ prog_data->flat_inputs = wm_prog_data.flat_inputs;
+ prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs;
prog_data->nr_params = wm_prog_data.base.nr_params;
for (unsigned i = 0; i < ARRAY_SIZE(param); i++)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 7ec5875..b895e39 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -223,6 +223,13 @@ struct brw_blorp_prog_data
*/
bool persample_msaa_dispatch;
+ /**
+ * Mask of which FS inputs are marked flat by the shader source. This is
+ * needed for setting up 3DSTATE_SF/SBE.
+ */
+ uint32_t flat_inputs;
+ unsigned num_varying_inputs;
+
/* The compiler will re-arrange push constants and store the upload order
* here. Given an index 'i' in the final upload buffer, param[i] gives the
* index in the uniform store. In other words, the value to be uploaded can
@@ -249,7 +256,6 @@ struct brw_blorp_params
};
bool color_write_disable[4];
struct brw_blorp_wm_push_constants wm_push_consts;
- unsigned num_varyings;
unsigned num_draw_buffers;
unsigned num_layers;
uint32_t wm_prog_kernel;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 4d73d04..d9f8c34 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -567,16 +567,22 @@ static void
gen6_blorp_emit_sf_config(struct brw_context *brw,
const struct brw_blorp_params *params)
{
+ const unsigned num_varyings =
+ params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
+
BEGIN_BATCH(20);
OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
- OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
+ OUT_BATCH(num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
BRW_SF_URB_ENTRY_READ_OFFSET <<
GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
OUT_BATCH(0); /* dw2 */
OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
- for (int i = 0; i < 16; ++i)
+ for (int i = 0; i < 13; ++i)
OUT_BATCH(0);
+ OUT_BATCH(params->wm_prog_data ? params->wm_prog_data->flat_inputs : 0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 270fe57..58bf9e9 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -442,15 +442,21 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
/* 3DSTATE_SBE */
{
+ const unsigned num_varyings =
+ params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
+
BEGIN_BATCH(14);
OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
- params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
+ num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
BRW_SF_URB_ENTRY_READ_OFFSET <<
GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
- for (int i = 0; i < 12; ++i)
+ for (int i = 0; i < 9; ++i)
OUT_BATCH(0);
+ OUT_BATCH(params->wm_prog_data ? params->wm_prog_data->flat_inputs : 0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
ADVANCE_BATCH();
}
}
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index a9a400d..6de9b73 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -294,22 +294,31 @@ static void
gen8_blorp_emit_sbe_state(struct brw_context *brw,
const struct brw_blorp_params *params)
{
+ const unsigned num_varyings = params->wm_prog_data->num_varying_inputs;
+
/* 3DSTATE_SBE */
{
const unsigned sbe_cmd_length = brw->gen == 8 ? 4 : 6;
BEGIN_BATCH(sbe_cmd_length);
OUT_BATCH(_3DSTATE_SBE << 16 | (sbe_cmd_length - 2));
OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
- params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
+ num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
BRW_SF_URB_ENTRY_READ_OFFSET <<
GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT |
GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET);
OUT_BATCH(0);
- OUT_BATCH(0);
+ OUT_BATCH(params->wm_prog_data->flat_inputs);
if (sbe_cmd_length >= 6) {
- OUT_BATCH(GEN9_SBE_ACTIVE_COMPONENT_XYZW << (0 << 1));
+ /* Fragment coordinates are always enabled. */
+ uint32_t dw4 = (GEN9_SBE_ACTIVE_COMPONENT_XYZW << (0 << 1));
+
+ for (unsigned i = 0; i < num_varyings; ++i) {
+ dw4 |= (GEN9_SBE_ACTIVE_COMPONENT_XYZW << ((i + 1) << 1));
+ }
+
+ OUT_BATCH(dw4);
OUT_BATCH(0);
}
ADVANCE_BATCH();
--
2.5.5
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