[Mesa-dev] [PATCH] i965/sklgt4: Implement depth/timestamp write w/a

[Anuj Phogat]

On Thu, May 26, 2016 at 11:04 AM, Ben Widawsky
<benjamin.widawsky at intel.com> wrote:
> From: Ben Widawsky <ben at bwidawsk.net>
>
> The stated bug describes a scenario in which a post sync write operation for
> depth or timestamp can be ignored. There are two workarounds suggested, the
> first and easier is to simply do a cs stall when we do these type of writes.
> The second option is to do a PIPE_CONTROL flush after the post sync but before
> the data is required.
>
> Generally, I believe the data written out is consumed by the application on the
> CPU side and so doing the easier of the two is ideal. Furthermore, these queries
> aren't tremendously common in the perf sensitive apps I have looked at. However,
> there could be cases where a shader stage might directly consume the data, and
> as a result option 2 may be desirable.
>
> This patch goes with the easier solution for now.
>
> gen9lp bug_de_id=2137196
>
> By itself, this does *not* fix any of the GT4 hangs we're currently
> experiencing.
>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  src/mesa/drivers/dri/i965/brw_queryobj.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
> index f32721b..7baa213 100644
> --- a/src/mesa/drivers/dri/i965/brw_queryobj.c
> +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
> @@ -56,7 +56,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
>                                    PIPE_CONTROL_STALL_AT_SCOREBOARD);
>     }
>
> -   brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_TIMESTAMP,
> +   uint32_t flags = PIPE_CONTROL_WRITE_TIMESTAMP;
> +
> +   if (brw->gen == 9 && brw->gt == 4)
> +      flags |= PIPE_CONTROL_CS_STALL;
> +
> +   brw_emit_pipe_control_write(brw, flags,
>                                 query_bo, idx * sizeof(uint64_t), 0, 0);
>  }
>
> @@ -66,9 +71,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
>  void
>  brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
>  {
> -   brw_emit_pipe_control_write(brw,
> -                               PIPE_CONTROL_WRITE_DEPTH_COUNT |
> -                               PIPE_CONTROL_DEPTH_STALL,
> +   uint32_t flags = PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_DEPTH_STALL;
> +
> +   if (brw->gen == 9 && brw->gt == 4)
> +      flags |= PIPE_CONTROL_CS_STALL;
> +
> +   brw_emit_pipe_control_write(brw, flags,
>                                 query_bo, idx * sizeof(uint64_t),
>                                 0, 0);
>  }
> --
> 2.8.3
>
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Verified the workaround in graphics specs.

Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>