[Mesa-dev] [PATCH 1/2] radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0

[Alex Deucher]

On Thu, May 26, 2016 at 5:51 PM, Marek Olšák <maraeo at gmail.com> wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> It's not needed since it was fixed in the kernel.

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  src/gallium/drivers/radeonsi/si_hw_context.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
> index dcf206d..6221f1c 100644
> --- a/src/gallium/drivers/radeonsi/si_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/si_hw_context.c
> @@ -116,8 +116,9 @@ void si_context_gfx_flush(void *context, unsigned flags,
>
>         ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
>                         SI_CONTEXT_PS_PARTIAL_FLUSH;
> -       /* The kernel doesn't flush TC for VI correctly (need TC_WB_ACTION_ENA). */
> -       if (ctx->b.chip_class == VI)
> +
> +       /* DRM 3.1.0 doesn't flush TC for VI correctly. */
> +       if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
>                 ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
>                                 SI_CONTEXT_INV_VMEM_L1;
>
> --
> 2.7.4
>
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