[Mesa-dev] [PATCH 19/25] i965/fs: Teach compute_to_mrf about the COMPR4 address transformation.
Francisco Jerez
currojerez at riseup.net
Sat May 28 02:06:00 UTC 2016
This will be required to correctly transform the destination of 8-wide
instructions that write a single GRF of a VGRF to MRF copy marked
COMPR4.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 7caf3ec..4062ea2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2909,8 +2909,30 @@ fs_visitor::compute_to_mrf()
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
if (regions_overlap(scan_inst->dst, scan_inst->regs_written * REG_SIZE,
inst->src[0], inst->regs_read(0) * REG_SIZE)) {
+ const unsigned rel_offset = (reg_offset(scan_inst->dst) -
+ reg_offset(inst->src[0])) / REG_SIZE;
+
+ if (inst->dst.nr & BRW_MRF_COMPR4) {
+ /* Apply the same address transformation done by the hardware
+ * for COMPR4 MRF writes.
+ */
+ assert(rel_offset < 2);
+ scan_inst->dst.nr = inst->dst.nr + rel_offset * 4;
+
+ /* Clear the COMPR4 bit if the generating instruction is not
+ * compressed.
+ */
+ if (scan_inst->regs_written < 2)
+ scan_inst->dst.nr &= ~BRW_MRF_COMPR4;
+
+ } else {
+ /* Calculate the MRF number the result of this instruction is
+ * ultimately written to.
+ */
+ scan_inst->dst.nr = inst->dst.nr + rel_offset;
+ }
+
scan_inst->dst.file = MRF;
- scan_inst->dst.nr = inst->dst.nr;
scan_inst->dst.reg_offset = 0;
scan_inst->saturate |= inst->saturate;
break;
--
2.7.3
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