[Mesa-dev] [v2 23/26] i965: Restructure fast clear eligibility decision

[Jason Ekstrand]

Much better.  Thanks!

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

On Tue, Nov 1, 2016 at 8:03 AM, Topi Pohjolainen <topi.pohjolainen at gmail.com
> wrote:

> From: Ben Widawsky <ben at bwidawsk.net>
>
> v2 (Jason):
>    - Use PRM citation for SKL now that it is available
>    - Also return false for gen < 8 mipmapped/arrayed
>
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 51
> +++++++++++++++++++--------
>  1 file changed, 37 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 32d8094..39ac86d 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -226,30 +226,53 @@ intel_miptree_supports_non_msrt_fast_clear(struct
> brw_context *brw,
>
>     if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
>        return false;
> -   if (mt->first_level != 0 || mt->last_level != 0) {
> -      if (brw->gen >= 8) {
> -         perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
> -                    mt->logical_width0, mt->logical_height0,
> mt->last_level);
> -      }
>
> -      return false;
> -   }
> +   const bool mip_mapped = mt->first_level != 0 || mt->last_level != 0;
> +   const bool arrayed = mt->physical_depth0 != 1;
>
> -   /* Check for layered surfaces. */
> -   if (mt->physical_depth0 != 1) {
> +   if (arrayed) {
>         /* Multisample surfaces with the CMS layout are not layered
> surfaces,
>          * yet still have physical_depth0 > 1. Assert that we don't
>          * accidentally reject a multisampled surface here. We should have
>          * rejected it earlier by explicitly checking the sample count.
>          */
>        assert(mt->num_samples <= 1);
> +   }
>
> -      if (brw->gen >= 8) {
> -         perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
> -                    mt->logical_width0, mt->logical_height0,
> -                    mt->physical_depth0);
> -      }
> +   /* Handle the hardware restrictions...
> +    *
> +    * All GENs have the following restriction: "MCS buffer for non-MSRT is
> +    * supported only for RT formats 32bpp, 64bpp, and 128bpp."
> +    *
> +    * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
> +    * Non-MultiSampler Render Target Restrictions) Support is for
> +    * non-mip-mapped and non-array surface types only.
> +    *
> +    * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
> +    * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
> +    * surfaces are supported with MCS buffer layout with these alignments
> in
> +    * the RT space: Horizontal Alignment = 256 and Vertical Alignment =
> 128.
> +    *
> +    * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
> +    * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
> +    * surfaces are supported with MCS buffer layout with these alignments
> in
> +    * the RT space: Horizontal Alignment = 128 and Vertical Alignment =
> 64.
> +    */
> +   if (brw->gen < 8 && (mip_mapped || arrayed))
> +      return false;
> +
> +   /* Not implemented yet. */
> +   if (mip_mapped) {
> +      perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
> +                 mt->logical_width0, mt->logical_height0, mt->last_level);
> +      return false;
> +   }
>
> +   /* Not implemented yet. */
> +   if (arrayed) {
> +      perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
> +                 mt->logical_width0, mt->logical_height0,
> +                 mt->physical_depth0);
>        return false;
>     }
>
> --
> 2.5.5
>
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