[Mesa-dev] [PATCH 1/2] i965/vec4: Fail compilation if we run out of registers during payload setup
Iago Toral Quiroga
itoral at igalia.com
Wed Nov 2 15:13:06 UTC 2016
Right now, if this happens we trigger an assertion when we try to create
a GRF register > 128. Let the backend compiler fail the compilation in this
case. For things like geometry shaders, this can trigger a compilation
using interleaved attribute setup which might even help get the shader to
compile successfully.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 6d487da..1fb65f3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1595,13 +1595,19 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
}
-static inline struct brw_reg
-attribute_to_hw_reg(int attr, bool interleaved)
+static inline bool
+attribute_to_hw_reg(int attr, bool interleaved, struct brw_reg *reg)
{
+ int grf = interleaved ? attr / 2 : attr;
+ if (grf >= BRW_MAX_GRF)
+ return false;
+
if (interleaved)
- return stride(brw_vec4_grf(attr / 2, (attr % 2) * 4), 0, 4, 1);
+ *reg = stride(brw_vec4_grf(attr / 2, (attr % 2) * 4), 0, 4, 1);
else
- return brw_vec8_grf(attr, 0);
+ *reg = brw_vec8_grf(attr, 0);
+
+ return true;
}
@@ -1635,7 +1641,12 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
*/
assert(grf != 0);
- struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
+ struct brw_reg reg;
+ if (!attribute_to_hw_reg(grf, interleaved, ®)) {
+ failed = true;
+ return;
+ }
+
reg.swizzle = inst->src[i].swizzle;
reg.type = inst->src[i].type;
if (inst->src[i].abs)
@@ -2047,6 +2058,9 @@ vec4_visitor::run()
setup_payload();
+ if (failed)
+ return false;
+
if (unlikely(INTEL_DEBUG & DEBUG_SPILL_VEC4)) {
/* Debug of register spilling: Go spill everything. */
const int grf_count = alloc.count;
--
2.7.4
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