[Mesa-dev] [PATCH 5/5] radeonsi: fix r600_texture::tc_compatible_htile

[Nicolai Hähnle]

The series is

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 09.11.2016 13:09, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> htile_size is now always non-zero if HTILE is allocated.
>
> It seems to have caused no issues.
> ---
>  src/gallium/drivers/radeon/r600_texture.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
> index 6933304..97673ee 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -1000,23 +1000,23 @@ r600_texture_create_object(struct pipe_screen *screen,
>  	resource->b.vtbl = &r600_texture_vtbl;
>  	pipe_reference_init(&resource->b.b.reference, 1);
>  	resource->b.b.screen = screen;
>
>  	/* don't include stencil-only formats which we don't support for rendering */
>  	rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
>
>  	rtex->surface = *surface;
>  	rtex->size = rtex->surface.surf_size;
>
> -	rtex->tc_compatible_htile = rtex->surface.htile_size != 0;
> -	assert(!!(rtex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) ==
> -	       rtex->tc_compatible_htile);
> +	rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
> +				    (rtex->surface.flags &
> +				     RADEON_SURF_TC_COMPATIBLE_HTILE);
>
>  	/* TC-compatible HTILE only supports Z32_FLOAT. */
>  	if (rtex->tc_compatible_htile)
>  		rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
>  	else
>  		rtex->db_render_format = base->format;
>
>  	/* Tiled depth textures utilize the non-displayable tile order.
>  	 * This must be done after r600_setup_surface.
>  	 * Applies to R600-Cayman. */
>