[Mesa-dev] [PATCH 06/20] anv/pipeline: Unify 3DSTATE_VS emission
Jason Ekstrand
jason at jlekstrand.net
Sat Nov 12 21:34:48 UTC 2016
---
src/intel/vulkan/gen7_pipeline.c | 29 +-----------
src/intel/vulkan/gen8_pipeline.c | 57 ++---------------------
src/intel/vulkan/genX_pipeline_util.h | 85 +++++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 82 deletions(-)
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 2c96a8d..d747c51 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -85,8 +85,6 @@ genX(graphics_pipeline_create)(
emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
- const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
-
#if 0
/* From gen7_vs_state.c */
@@ -106,32 +104,7 @@ genX(graphics_pipeline_create)(
gen7_emit_vs_workaround_flush(brw);
#endif
- assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
- const struct anv_shader_bin *vs_bin =
- pipeline->shaders[MESA_SHADER_VERTEX];
- anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
- vs.KernelStartPointer = vs_bin->kernel.offset;
-
- vs.ScratchSpaceBasePointer = (struct anv_address) {
- .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
- MESA_SHADER_VERTEX,
- vs_prog_data->base.base.total_scratch),
- .offset = 0,
- };
- vs.PerThreadScratchSpace = scratch_space(&vs_prog_data->base.base);
-
- vs.DispatchGRFStartRegisterForURBData =
- vs_prog_data->base.base.dispatch_grf_start_reg;
-
- vs.SamplerCount = get_sampler_count(vs_bin);
- vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
-
- vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
- vs.VertexURBEntryReadOffset = 0;
- vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
- vs.StatisticsEnable = true;
- vs.FunctionEnable = true;
- }
+ emit_3dstate_vs(pipeline);
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index f023d6c..827ee51 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -59,7 +59,6 @@ genX(graphics_pipeline_create)(
struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
struct anv_pipeline *pipeline;
VkResult result;
- uint32_t offset, length;
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
@@ -120,8 +119,8 @@ genX(graphics_pipeline_create)(
const struct anv_shader_bin *gs_bin =
pipeline->shaders[MESA_SHADER_GEOMETRY];
- offset = 1;
- length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
+ uint32_t offset = 1;
+ uint32_t length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
gs.SingleProgramFlow = false;
@@ -171,57 +170,7 @@ genX(graphics_pipeline_create)(
}
}
- const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
- assert(!vs_prog_data->base.base.use_alt_mode);
- /* Skip the VUE header and position slots */
- offset = 1;
- length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
-
- assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
- const struct anv_shader_bin *vs_bin =
- pipeline->shaders[MESA_SHADER_VERTEX];
- anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
- vs.KernelStartPointer = vs_bin->kernel.offset;
- vs.SingleVertexDispatch = false;
- vs.VectorMaskEnable = false;
-
- vs.SamplerCount = get_sampler_count(vs_bin);
- vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
-
- vs.ThreadDispatchPriority = false;
- vs.FloatingPointMode = IEEE754;
- vs.IllegalOpcodeExceptionEnable = false;
- vs.AccessesUAV = false;
- vs.SoftwareExceptionEnable = false;
-
- vs.ScratchSpaceBasePointer = (struct anv_address) {
- .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
- MESA_SHADER_VERTEX,
- vs_prog_data->base.base.total_scratch),
- .offset = 0,
- };
- vs.PerThreadScratchSpace = scratch_space(&vs_prog_data->base.base);
-
- vs.DispatchGRFStartRegisterForURBData =
- vs_prog_data->base.base.dispatch_grf_start_reg;
-
- vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
- vs.VertexURBEntryReadOffset = 0;
-
- vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
- vs.StatisticsEnable = true;
- vs.SIMD8DispatchEnable =
- vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
- vs.VertexCacheDisable = false;
- vs.FunctionEnable = true;
-
- vs.VertexURBEntryOutputReadOffset = offset;
- vs.VertexURBEntryOutputLength = length;
-
- /* TODO */
- vs.UserClipDistanceClipTestEnableBitmask = 0;
- vs.UserClipDistanceCullTestEnableBitmask = 0;
- }
+ emit_3dstate_vs(pipeline);
const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index 18b4877..4fa96c8 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -968,4 +968,89 @@ get_binding_table_entry_count(const struct anv_shader_bin *bin)
return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
}
+static inline struct anv_address
+get_scratch_address(struct anv_pipeline *pipeline,
+ gl_shader_stage stage,
+ const struct anv_shader_bin *bin)
+{
+ return (struct anv_address) {
+ .bo = anv_scratch_pool_alloc(pipeline->device,
+ &pipeline->device->scratch_pool,
+ stage, bin->prog_data->total_scratch),
+ .offset = 0,
+ };
+}
+
+static inline uint32_t
+get_scratch_space(const struct anv_shader_bin *bin)
+{
+ return ffs(bin->prog_data->total_scratch / 2048);
+}
+
+static inline uint32_t
+get_urb_output_offset()
+{
+ /* Skip the VUE header and position slots */
+ return 1;
+}
+
+static inline uint32_t
+get_urb_output_length(const struct anv_shader_bin *bin)
+{
+ const struct brw_vue_prog_data *prog_data =
+ (const struct brw_vue_prog_data *)bin->prog_data;
+
+ return (prog_data->vue_map.num_slots + 1) / 2 - get_urb_output_offset();
+}
+
+static void
+emit_3dstate_vs(struct anv_pipeline *pipeline)
+{
+ const struct gen_device_info *devinfo = &pipeline->device->info;
+ const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
+ const struct anv_shader_bin *vs_bin =
+ pipeline->shaders[MESA_SHADER_VERTEX];
+
+ assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
+
+ anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
+ vs.FunctionEnable = true;
+ vs.StatisticsEnable = true;
+ vs.KernelStartPointer = vs_bin->kernel.offset;
+#if GEN_GEN >= 8
+ vs.SIMD8DispatchEnable =
+ vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
+#endif
+
+ assert(!vs_prog_data->base.base.use_alt_mode);
+ vs.SingleVertexDispatch = false;
+ vs.VectorMaskEnable = false;
+ vs.SamplerCount = get_sampler_count(vs_bin);
+ vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
+ vs.FloatingPointMode = IEEE754;
+ vs.IllegalOpcodeExceptionEnable = false;
+ vs.SoftwareExceptionEnable = false;
+ vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
+ vs.VertexCacheDisable = false;
+
+ vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
+ vs.VertexURBEntryReadOffset = 0;
+ vs.DispatchGRFStartRegisterForURBData =
+ vs_prog_data->base.base.dispatch_grf_start_reg;
+
+#if GEN_GEN >= 8
+ vs.VertexURBEntryOutputReadOffset = get_urb_output_offset();
+ vs.VertexURBEntryOutputLength = get_urb_output_length(vs_bin);
+
+ /* TODO */
+ vs.UserClipDistanceClipTestEnableBitmask = 0;
+ vs.UserClipDistanceCullTestEnableBitmask = 0;
+#endif
+
+ vs.PerThreadScratchSpace = get_scratch_space(vs_bin);
+ vs.ScratchSpaceBasePointer =
+ get_scratch_address(pipeline, MESA_SHADER_VERTEX, vs_bin);
+ }
+}
+
#endif /* GENX_PIPELINE_UTIL_H */
--
2.5.0.400.gff86faf
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