[Mesa-dev] [PATCH 31/59] st/glsl_to_tgsi: add support for 64-bit integers. (v2)

[Nicolai Hähnle]

On 10.11.2016 23:59, Ian Romanick wrote:
> On 10/27/2016 06:32 AM, Nicolai Hähnle wrote:
>> On 26.10.2016 02:59, Ian Romanick wrote:
>>> From: Dave Airlie <airlied at redhat.com>
>>>
>>> v2: add conversion opcodes.
>>>
>>> v3 (idr): Rebase on replacemtn of TGSI_OPCODE_I2U64 with
>>> TGSI_OPCODE_I2I64.
>>>
>>> Signed-off-by: Dave Airlie <airlied at redhat.com>
>>> ---
>>>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 217
>>> ++++++++++++++++++++++++++---
>>>  1 file changed, 198 insertions(+), 19 deletions(-)
>>>
>> [snip]
>>> +   case ir_unop_u2i64:
>>> +   case ir_unop_u2u64:
>>> +   case ir_unop_b2i64:
>>> +   case ir_unop_b2u64: {
>>> +      st_src_reg temp = get_temp(glsl_type::uvec4_type);
>>> +      st_dst_reg temp_dst = st_dst_reg(temp);
>>> +      unsigned orig_swz = op[0].swizzle;
>>> +      /*
>>> +       * To convert unsigned to 64-bit:
>>> +       * zero Y channel, copy X channel.
>>> +       */
>>> +      temp_dst.writemask = WRITEMASK_Y;
>>> +      if (vector_elements > 1)
>>> +         temp_dst.writemask |= WRITEMASK_W;
>>> +      emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
>>> +      temp_dst.writemask = WRITEMASK_X;
>>> +      if (vector_elements > 1)
>>> +          temp_dst.writemask |= WRITEMASK_Z;
>>> +      op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0),
>>> GET_SWZ(orig_swz, 0),
>>> +                                    GET_SWZ(orig_swz, 1),
>>> GET_SWZ(orig_swz, 1));
>>> +      if (ir->operation == ir_unop_u2i64 || ir->operation ==
>>> ir_unop_u2u64)
>>> +         emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
>>> +      else
>>> +         emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
>>> st_src_reg_for_int(1));
>>> +      result_src = temp;
>>> +      result_src.type = GLSL_TYPE_UINT64;
>>> +      if (vector_elements > 2) {
>>> +         st_src_reg temp = get_temp(glsl_type::uvec4_type);
>>> +         st_dst_reg temp_dst = st_dst_reg(temp);
>>> +         temp_dst.writemask = WRITEMASK_Y;
>>> +         if (vector_elements > 3)
>>> +            temp_dst.writemask |= WRITEMASK_W;
>>> +         emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
>>> +
>>> +         temp_dst.writemask = WRITEMASK_X;
>>> +         if (vector_elements > 3)
>>> +            temp_dst.writemask |= WRITEMASK_Z;
>>> +         op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
>>> GET_SWZ(orig_swz, 2),
>>> +                                       GET_SWZ(orig_swz, 3),
>>> GET_SWZ(orig_swz, 3));
>>> +         if (ir->operation == ir_unop_u2i64 || ir->operation ==
>>> ir_unop_u2u64)
>>> +            emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
>>> +         else
>>> +            emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
>>> st_src_reg_for_int(1));
>>> +      }
>>> +      break;
>>> +   }
>>
>> This part is suspicious. It looks like the top two vector elements are
>> written into a temporary register that isn't used anywhere.
>
> Uh... I have no idea about this code. :)  All of the Gallium patches
> were written by Dave, and I've just been rebasing them.

Sure, no problem. I can take care of those patches when the rest of the 
series lands, I'd just ask you not to push them as-is. Especially the 
pipe cap patch _really_ shouldn't land in master as-is :)

Thanks,
Nicolai