[Mesa-dev] [PATCH 02/14] swr: [rasterizer memory] round up when dividing by block sizes

[Cherniak, Bruce]

Sorry, yes, I was aware of the updated patch.  What I meant (in not enough words apparently) is that a change like this could affect other users of the core and need to go through full CI.  We’ve run CI on the updated patch and it passes.

So, yes, please go ahead and send that one out.  Reviewing it will be quick with testing already done.

On Nov 14, 2016, at 10:50 PM, Ilia Mirkin <imirkin at alum.mit.edu<mailto:imirkin at alum.mit.edu>> wrote:


I think you're aware, but I actually have an updated version of this patch on my branch. Let me know if you want me to send it out.

The issue is that the texture width/height need not be a multiple of the format's block size. However mip sizes are computed based on that unrounded size.

On Nov 14, 2016 8:45 PM, "Cherniak, Bruce" <bruce.cherniak at intel.com<mailto:bruce.cherniak at intel.com>> wrote:
We need to run this through CI for all core users.

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin <imirkin at alum.mit.edu<mailto:imirkin at alum.mit.edu>> wrote:
>
> There's no guarantee that mip width/height will be a multiple of the
> compressed block size. Make sure to round up when dividing.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu<mailto:imirkin at alum.mit.edu>>
> ---
>
> Note - I don't actually need this. An earlier version of my patches needed
> something like this. However since it's a real fix, I figured I'd include
> it here.
>
> .../drivers/swr/rasterizer/memory/TilingFunctions.h       | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> index 0694a99..710bfb3 100644
> --- a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> +++ b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> @@ -276,7 +276,10 @@ INLINE void ComputeLODOffset1D(
>         uint32_t curWidth = baseWidth;
>         // translate mip width from pixels to blocks for block compressed formats
>         // @note hAlign is already in blocks for compressed formats so no need to convert
> -        if (info.isBC) curWidth /= info.bcWidth;
> +        if (info.isBC)
> +        {
> +            curWidth = GFX_ALIGN(curWidth, info.bcWidth) / info.bcWidth;
> +        }
>
>         offset = GFX_ALIGN(curWidth, hAlign);
>         for (uint32_t l = 1; l < lod; ++l)
> @@ -314,7 +317,10 @@ INLINE void ComputeLODOffsetX(
>         uint32_t curWidth = baseWidth;
>         // convert mip width from pixels to blocks for block compressed formats
>         // @note hAlign is already in blocks for compressed formats so no need to convert
> -        if (info.isBC) curWidth /= info.bcWidth;
> +        if (info.isBC)
> +        {
> +            curWidth = GFX_ALIGN(curWidth, info.bcWidth) / info.bcWidth;
> +        }
>
>         curWidth = std::max<uint32_t>(curWidth >> 1, 1U);
>         curWidth = GFX_ALIGN(curWidth, hAlign);
> @@ -352,7 +358,10 @@ INLINE void ComputeLODOffsetY(
>
>         // translate mip height from pixels to blocks for block compressed formats
>         // @note VAlign is already in blocks for compressed formats so no need to convert
> -        if (info.isBC) mipHeight /= info.bcHeight;
> +        if (info.isBC)
> +        {
> +            mipHeight = GFX_ALIGN(mipHeight, info.bcHeight) / info.bcHeight;
> +        }
>
>         for (uint32_t l = 1; l <= lod; ++l)
>         {
> --
> 2.7.3
>
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