[Mesa-dev] [PATCH 01/20] gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

FORCE_TILING should disable it. It has no effect now, but that may change
soon.
---
 src/gallium/drivers/radeon/r600_texture.c      | 2 ++
 src/gallium/drivers/radeon/radeon_winsys.h     | 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 4 +++-
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 97673ee..259ff36 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -246,20 +246,22 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 		       ptex->array_size == 1 &&
 		       ptex->depth0 == 1 &&
 		       ptex->last_level == 0 &&
 		       !(flags & RADEON_SURF_Z_OR_SBUFFER));
 
 		flags |= RADEON_SURF_SCANOUT;
 	}
 
 	if (is_imported)
 		flags |= RADEON_SURF_IMPORTED;
+	if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
+		flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
 	r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
 				      array_mode, surface);
 	if (r) {
 		return r;
 	}
 
 	if (pitch_in_bytes_override &&
 	    pitch_in_bytes_override != surface->level[0].nblk_x * bpe) {
 		/* old ddx on evergreen over estimate alignment for 1d, only 1 level
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 3e30e95..3027c4a 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -274,20 +274,21 @@ enum radeon_micro_mode {
 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_SCANOUT                     (1 << 16)
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
+#define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 
 struct radeon_surf_level {
     uint64_t                    offset;
     uint64_t                    slice_size;
     uint64_t                    dcc_offset;
     uint64_t                    dcc_fast_clear_size;
     uint16_t                    nblk_x;
     uint16_t                    nblk_y;
     enum radeon_surf_mode       mode;
 };
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index d65dae7..d8ab28b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -395,21 +395,23 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    AddrSurfInfoIn.flags.cube = tex->target == PIPE_TEXTURE_CUBE;
    AddrSurfInfoIn.flags.fmask = (flags & RADEON_SURF_FMASK) != 0;
    AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
    AddrSurfInfoIn.flags.pow2Pad = tex->last_level > 0;
    AddrSurfInfoIn.flags.tcCompatible = (flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 
    /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
     * requested, because TC-compatible HTILE requires 2D tiling.
     */
    AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
-                                        !(flags & RADEON_SURF_FMASK);
+                                        !AddrSurfInfoIn.flags.fmask &&
+                                        tex->nr_samples <= 1 &&
+                                        (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
 
    /* DCC notes:
     * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
     *   with samples >= 4.
     * - Mipmapped array textures have low performance (discovered by a closed
     *   driver team).
     */
    AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
                                         !(flags & RADEON_SURF_Z_OR_SBUFFER) &&
                                         !(flags & RADEON_SURF_DISABLE_DCC) &&
-- 
2.7.4