[Mesa-dev] [v2 08/17] i965: Add plumbing for fast clear layer/level details
Topi Pohjolainen
topi.pohjolainen at gmail.com
Wed Nov 23 09:16:07 UTC 2016
Until now fast clear has been supported only for non-layered and
non-mipmapped buffers. However, from gen8 onwards there is hardware
support also for layered/mipmapped. Once this is enabled, fast clear
operations target specific layer/level and call for the state to be
tracked in the same granularity. This is the first step providing
the details from callers to the state tracking.
Patch introduces new interface for reading and writing the state
hiding the upcoming bookkeeping changes in the call sites. There is
bunch of sanity checks added that will be relaxed per hardware
generation later on when the actual functionality is enabled.
v2: Rebased on top current master setting the state in
blorp_surf_for_miptree().
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net> (v1)
---
src/mesa/drivers/dri/i965/brw_blorp.c | 17 ++++++++----
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 ++++++++++++++++--------
2 files changed, 35 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 749354e..44ae26e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -218,7 +218,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
*level, start_layer + i, flags);
}
- assert(mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED);
+ assert(!intel_miptree_has_color_unresolved(mt, *level, 1,
+ start_layer, num_layers));
surf->aux_usage = ISL_AUX_USAGE_NONE;
}
}
@@ -813,8 +814,12 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
!brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
can_fast_clear = false;
+ const unsigned logical_layer = irb_logical_mt_layer(irb);
const bool is_lossless_compressed = intel_miptree_is_lossless_compressed(
brw, irb->mt);
+ const enum intel_fast_clear_state fast_clear_state =
+ intel_miptree_get_fast_clear_state(irb->mt, irb->mt_level,
+ logical_layer);
if (can_fast_clear) {
union gl_color_union override_color =
@@ -846,7 +851,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* it is available without consulting the surface state.
*/
if ((!color_updated || !is_lossless_compressed) &&
- irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
+ fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
return true;
/* If the MCS buffer hasn't been allocated yet, we need to allocate
@@ -864,7 +869,6 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
}
}
- const unsigned logical_layer = irb_logical_mt_layer(irb);
const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
/* We can't setup the blorp_surf until we've allocated the MCS above */
@@ -893,7 +897,9 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
* redundant clears.
*/
- irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
+ intel_miptree_set_fast_clear_state(irb->mt, irb->mt_level,
+ logical_layer, num_layers,
+ INTEL_FAST_CLEAR_STATE_CLEAR);
} else {
DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
@@ -980,7 +986,8 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
resolve_op);
blorp_batch_finish(&batch);
- mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
+ intel_miptree_set_fast_clear_state(mt, level, layer, 1,
+ INTEL_FAST_CLEAR_STATE_RESOLVED);
}
static void
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ec434c7..7fc0d0c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -441,20 +441,24 @@ brw_find_matching_rb(const struct gl_framebuffer *fb,
static inline bool
brw_texture_view_sane(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt, unsigned format)
+ const struct intel_mipmap_tree *mt,
+ const struct isl_view *view)
{
/* There are special cases only for lossless compression. */
if (!intel_miptree_is_lossless_compressed(brw, mt))
return true;
if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
- format))
+ view->format))
return true;
/* Logic elsewhere needs to take care to resolve the color buffer prior
* to sampling it as non-compressed.
*/
- if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)
+ const enum intel_fast_clear_state fast_clear_state =
+ intel_miptree_get_fast_clear_state(mt, view->base_level,
+ view->base_array_layer);
+ if (fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)
return false;
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
@@ -473,15 +477,20 @@ brw_texture_view_sane(const struct brw_context *brw,
static bool
brw_disable_aux_surface(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
+ const struct intel_mipmap_tree *mt,
+ const struct isl_view *view)
{
/* Nothing to disable. */
if (!mt->mcs_buf)
return false;
+ const bool is_unresolved = intel_miptree_has_color_unresolved(
+ mt, view->base_level, view->levels,
+ view->base_array_layer, view->array_len);
+
/* There are special cases only for lossless compression. */
if (!intel_miptree_is_lossless_compressed(brw, mt))
- return mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED;
+ return !is_unresolved;
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
const unsigned rb_index = brw_find_matching_rb(fb, mt);
@@ -499,13 +508,13 @@ brw_disable_aux_surface(const struct brw_context *brw,
*/
if (rb_index < fb->_NumColorDrawBuffers) {
if (brw->draw_aux_buffer_disabled[rb_index]) {
- assert(mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED);
+ assert(!is_unresolved);
}
return brw->draw_aux_buffer_disabled[rb_index];
}
- return mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED;
+ return !is_unresolved;
}
void
@@ -625,10 +634,10 @@ brw_update_texture_surface(struct gl_context *ctx,
obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
view.usage |= ISL_SURF_USAGE_CUBE_BIT;
- assert(brw_texture_view_sane(brw, mt, format));
+ assert(brw_texture_view_sane(brw, mt, &view));
- const int flags =
- brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0;
+ const int flags = brw_disable_aux_surface(brw, mt, &view) ?
+ INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
tex_mocs[brw->gen],
surf_offset, surf_index,
@@ -1749,8 +1758,11 @@ update_image_surface(struct brw_context *brw,
};
const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
+ const enum intel_fast_clear_state fast_clear_state =
+ intel_miptree_get_fast_clear_state(mt, view.base_level,
+ view.base_array_layer);
const int flags =
- mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED ?
+ fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED ?
INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
tex_mocs[brw->gen],
--
2.5.5
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