[Mesa-dev] [PATCH] radv: Simple inter stage shader optimization

[Bas Nieuwenhuizen]

Remove vs exports if the ps doesn't use them.

Longer term we will probably want to do the optimizations between
stages in nir, but this seems simple enough for the short term.

Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
---
 src/amd/common/ac_nir_to_llvm.c |  3 ++-
 src/amd/common/ac_nir_to_llvm.h |  1 +
 src/amd/vulkan/radv_pipeline.c  | 32 +++++++++++++++++---------------
 3 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c68cb9c..e4acda7 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4240,7 +4240,8 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
 						       (1ull << VARYING_SLOT_CLIP_DIST1) |
 						       (1ull << VARYING_SLOT_CULL_DIST0) |
 						       (1ull << VARYING_SLOT_CULL_DIST1));
-
+	ctx->output_mask = (ctx->output_mask & ~(0xFFFFFFFFull << VARYING_SLOT_VAR0)) |
+	                   (ctx->output_mask & ((uint64_t)ctx->options->key.vs.next_shader_inputs << VARYING_SLOT_VAR0));
 	if (clip_mask) {
 		LLVMValueRef slots[8];
 		unsigned j;
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index ca06d05..863ec5a 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -36,6 +36,7 @@ struct radv_pipeline_layout;
 
 struct ac_vs_variant_key {
 	uint32_t instance_rate_inputs;
+	uint32_t next_shader_inputs;
 };
 
 struct ac_fs_variant_key {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7d7d0c6..ae9aabe 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1309,21 +1309,8 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 
 	radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
 
-	/* */
-	if (modules[MESA_SHADER_VERTEX]) {
-		union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
-
-		pipeline->shaders[MESA_SHADER_VERTEX] =
-			 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
-					       pStages[MESA_SHADER_VERTEX]->pName,
-					       MESA_SHADER_VERTEX,
-					       pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
-					       pipeline->layout, &key, dump);
-
-		pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
-	}
-
-	if (!modules[MESA_SHADER_FRAGMENT]) {
+	if (!modules[MESA_SHADER_FRAGMENT] ||
+	    pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
 		nir_builder fs_b;
 		nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 		fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
@@ -1350,6 +1337,21 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 	if (fs_m.nir)
 		ralloc_free(fs_m.nir);
 
+	/* */
+	if (modules[MESA_SHADER_VERTEX]) {
+		union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
+		key.vs.next_shader_inputs = pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.input_mask;
+
+		pipeline->shaders[MESA_SHADER_VERTEX] =
+			 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
+					       pStages[MESA_SHADER_VERTEX]->pName,
+					       MESA_SHADER_VERTEX,
+					       pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
+					       pipeline->layout, &key, dump);
+
+		pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
+	}
+
 	radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
 	radv_pipeline_init_raster_state(pipeline, pCreateInfo);
 	radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
-- 
2.10.2