[Mesa-dev] [PATCH 2/4] intel/isl: Use row_pitch helpers in isl_surf_fill_state

[Jason Ekstrand]

---
 src/intel/isl/isl_surface_state.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 3bb0abd..27468b3 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -405,7 +405,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       /* For gen9 1-D textures, surface pitch is ignored */
       s.SurfacePitch = 0;
    } else {
-      s.SurfacePitch = info->surf->row_pitch - 1;
+      s.SurfacePitch = isl_surf_get_row_pitch_B(info->surf) - 1;
    }
 
 #if GEN_GEN >= 8
@@ -503,14 +503,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 
 #if GEN_GEN >= 7
    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
-      struct isl_tile_info tile_info;
-      isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);
-      uint32_t pitch_in_tiles =
-         info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
-
 #if GEN_GEN >= 8
       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
-      s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
+      s.AuxiliarySurfacePitch =
+         isl_surf_get_row_pitch_tl(dev, info->aux_surf) - 1;
       /* Auxiliary surfaces in ISL have compressed formats but the hardware
        * doesn't expect our definition of the compression, it expects qpitch
        * in units of samples on the main surface.
@@ -523,7 +519,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
              info->aux_usage == ISL_AUX_USAGE_CCS_D);
       s.MCSBaseAddress = info->aux_address,
-      s.MCSSurfacePitch = pitch_in_tiles - 1;
+      s.MCSSurfacePitch = isl_surf_get_row_pitch_tl(dev, info->aux_surf) - 1;
       s.MCSEnable = true;
 #endif
    }
-- 
2.5.0.400.gff86faf