[Mesa-dev] [PATCH 7/8] radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as well

[Nicolai Hähnle]

On 30.11.2016 15:01, Nicolai Hähnle wrote:
> On 30.11.2016 02:36, Marek Olšák wrote:
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> Internal docs don't mention it, but they also don't mention that the bug
>> has been fixed (like other CI bugs fixed in VI).
>>
>> Vulkan does this too.
>>
>> Cc: 13.0 <mesa-stable at lists.freedesktop.org>
>> ---
>>  src/gallium/drivers/radeon/r600_pipe_common.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
>> b/src/gallium/drivers/radeon/r600_pipe_common.c
>> index 15e8a12..bb4cd86 100644
>> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
>> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
>> @@ -95,21 +95,22 @@ void r600_gfx_write_event_eop(struct
>> r600_common_context *ctx,
>>                    unsigned event, unsigned event_flags,
>>                    unsigned data_sel,
>>                    struct r600_resource *buf, uint64_t va,
>>                    uint32_t old_fence, uint32_t new_fence)
>>  {
>>      struct radeon_winsys_cs *cs = ctx->gfx.cs;
>>      unsigned op = EVENT_TYPE(event) |
>>                EVENT_INDEX(5) |
>>                event_flags;
>>
>> -    if (ctx->chip_class == CIK) {
>> +    if (ctx->chip_class == CIK ||
>> +        ctx->chip_class == VI) {
>
> This needs a corresponding change in r600_gfx_write_fence_dwords.
>
> Would be good to get a clarification from the HW team on this. Or maybe
> dig up the corresponding bug in the internal bug tracker? I vaguely
> recall seeing something in there, but maybe I'm getting it confused with
> another bug.

Never mind, from the dates it's pretty clear that this must affect VI as 
well.

The other function still needs to be adjusted though. With that change 
you can add my R-b to this patch as well.

Nicolai

> Nicolai
>
>>          /* Two EOP events are required to make all engines go idle
>>           * (and optional cache flushes executed) before the timestamp
>>           * is written.
>>           */
>>          radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
>>          radeon_emit(cs, op);
>>          radeon_emit(cs, va);
>>          radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
>>          radeon_emit(cs, old_fence); /* immediate data */
>>          radeon_emit(cs, 0); /* unused */
>>