[Mesa-dev] [PATCH] gallium/radeon/winsyses: set reasonable max_alloc_size

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

which is returned for GL_MAX_TEXTURE_BUFFER_SIZE.
It doesn't have any other use at the moment.
Bigger allocations are not rejected.

This fixes GL45-CTS.texture_buffer.texture_buffer_max_size on Bonaire.
---
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c     | 2 +-
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index c28e1ca..1deb8bd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -312,21 +312,21 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
    }
 
    /* Set which chips have dedicated VRAM. */
    ws->info.has_dedicated_vram =
       !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 
    /* Set hardware information. */
    ws->info.gart_size = gtt.heap_size;
    ws->info.vram_size = vram.heap_size;
    /* TODO: the kernel reports vram/gart.max_allocation == 251 MB (bug?) */
-   ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
+   ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.9;
    /* convert the shader clock from KHz to MHz */
    ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
    ws->info.max_se = ws->amdinfo.num_shader_engines;
    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
    ws->info.has_uvd = uvd.available_rings != 0;
    ws->info.uvd_fw_version =
          uvd.available_rings ? uvd_version : 0;
    ws->info.vce_fw_version =
          vce.available_rings ? vce_version : 0;
    ws->info.has_userptr = true;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index c7ceee2..515f5cc 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -366,21 +366,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
             &gem_info, sizeof(gem_info));
     if (retval) {
         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
                 retval);
         return false;
     }
     ws->info.gart_size = gem_info.gart_size;
     ws->info.vram_size = gem_info.vram_size;
 
-    ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
+    ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
     if (ws->info.drm_minor < 40)
         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 
     /* Get max clock frequency info and convert it to MHz */
     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
                          &ws->info.max_shader_clock);
     ws->info.max_shader_clock /= 1000;
 
     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
                          &ws->info.enabled_rb_mask);
-- 
2.7.4