[Mesa-dev] [PATCH 7/8] i965: get inputs read from nir info
Timothy Arceri
timothy.arceri at collabora.com
Wed Oct 5 06:32:33 UTC 2016
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
---
src/mesa/drivers/dri/i965/brw_curbe.c | 4 +++-
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/brw_interpolation_map.c | 3 ++-
src/mesa/drivers/dri/i965/brw_sf.c | 7 +++++--
src/mesa/drivers/dri/i965/brw_tcs.c | 8 +++++---
src/mesa/drivers/dri/i965/brw_tes.c | 10 ++++++----
src/mesa/drivers/dri/i965/brw_vs.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm.c | 14 +++++++++-----
src/mesa/drivers/dri/i965/gen6_sf_state.c | 4 +++-
src/mesa/drivers/dri/i965/gen8_sf_state.c | 5 ++++-
10 files changed, 39 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 02c4e38..9ef486c 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -50,6 +50,7 @@
*/
+#include "compiler/nir/nir.h"
#include "main/context.h"
#include "main/macros.h"
#include "main/enums.h"
@@ -324,7 +325,8 @@ emit:
* BRW_NEW_FRAGMENT_PROGRAM
*/
if (brw->gen == 4 && !brw->is_g4x &&
- (brw->fragment_program->Base.InputsRead & (1 << VARYING_SLOT_POS))) {
+ (brw->fragment_program->Base.nir->info.inputs_read &
+ (1 << VARYING_SLOT_POS))) {
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index cab67c9..df35651 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -302,7 +302,7 @@ brw_merge_inputs(struct brw_context *brw,
}
if (brw->gen < 8 && !brw->is_haswell) {
- GLbitfield64 mask = ctx->VertexProgram._Current->Base.InputsRead;
+ uint64_t mask = ctx->VertexProgram._Current->Base.nir->info.inputs_read;
/* Prior to Haswell, the hardware can't natively support GL_FIXED or
* 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_interpolation_map.c b/src/mesa/drivers/dri/i965/brw_interpolation_map.c
index 6d0a813..7ca3c05 100644
--- a/src/mesa/drivers/dri/i965/brw_interpolation_map.c
+++ b/src/mesa/drivers/dri/i965/brw_interpolation_map.c
@@ -22,6 +22,7 @@
*/
#include "brw_state.h"
+#include "compiler/nir/nir.h"
static char const *get_qual_name(int mode)
{
@@ -72,7 +73,7 @@ brw_setup_vue_interpolation(struct brw_context *brw)
if (varying == VARYING_SLOT_BFC0 || varying == VARYING_SLOT_BFC1)
frag_attrib = varying - VARYING_SLOT_BFC0 + VARYING_SLOT_COL0;
- if (!(fprog->Base.InputsRead & BITFIELD64_BIT(frag_attrib)))
+ if (!(fprog->Base.nir->info.inputs_read & BITFIELD64_BIT(frag_attrib)))
continue;
enum glsl_interp_mode mode = fprog->InterpQualifier[frag_attrib];
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index 6d8cd74..2090737 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -29,7 +29,7 @@
* Keith Whitwell <keithw at vmware.com>
*/
-
+#include "compiler/nir/nir.h"
#include "main/macros.h"
#include "main/mtypes.h"
#include "main/enums.h"
@@ -192,8 +192,11 @@ brw_upload_sf_prog(struct brw_context *brw)
if (key.do_point_sprite) {
key.point_sprite_coord_replace = ctx->Point.CoordReplace & 0xff;
}
- if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
+ if (brw->fragment_program->Base.nir->info.inputs_read &
+ BITFIELD64_BIT(VARYING_SLOT_PNTC)) {
key.do_point_coord = 1;
+ }
+
/*
* Window coordinates in a FBO are inverted, which means point
* sprite origin must be inverted, too.
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index ba0ab49..96fdcc9 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -316,8 +316,10 @@ void
brw_tcs_populate_key(struct brw_context *brw,
struct brw_tcs_prog_key *key)
{
- uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead;
- uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead;
+ uint64_t per_vertex_slots =
+ brw->tess_eval_program->Base.nir->info.inputs_read;
+ uint32_t per_patch_slots =
+ brw->tess_eval_program->Base.nir->info.patch_inputs_read;
struct brw_tess_ctrl_program *tcp =
(struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
@@ -353,7 +355,7 @@ brw_tcs_populate_key(struct brw_context *brw,
/* _NEW_TEXTURE */
brw_populate_sampler_prog_key_data(&brw->ctx, prog, &key->tex);
} else {
- key->outputs_written = tep->program.Base.InputsRead;
+ key->outputs_written = tep->program.Base.nir->info.inputs_read;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 965916c..fce7577 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -234,8 +234,10 @@ brw_tes_populate_key(struct brw_context *brw,
struct brw_tes_prog_key *key)
{
- uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead;
- uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead;
+ uint64_t per_vertex_slots =
+ brw->tess_eval_program->Base.nir->info.inputs_read;
+ uint32_t per_patch_slots =
+ brw->tess_eval_program->Base.nir->info.patch_inputs_read;
struct brw_tess_eval_program *tep =
(struct brw_tess_eval_program *) brw->tess_eval_program;
@@ -314,8 +316,8 @@ brw_tes_precompile(struct gl_context *ctx,
memset(&key, 0, sizeof(key));
key.program_string_id = btep->id;
- key.inputs_read = prog->InputsRead;
- key.patch_inputs_read = prog->PatchInputsRead;
+ key.inputs_read = prog->nir->info.inputs_read;
+ key.patch_inputs_read = prog->nir->info.patch_inputs_read;
if (shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
struct gl_program *tcp =
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 7768da8..199d124 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -152,7 +152,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
uint64_t outputs_written =
brw_vs_outputs_written(brw, key,
vp->program.Base.nir->info.outputs_written);
- prog_data.inputs_read = vp->program.Base.InputsRead;
+ prog_data.inputs_read = vp->program.Base.nir->info.inputs_read;
if (key->copy_edgeflag) {
prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index eb89b2b..3e36b44 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -543,9 +543,11 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
}
/* BRW_NEW_VUE_MAP_GEOM_OUT */
- if (brw->gen < 6 || _mesa_bitcount_64(fp->program.Base.InputsRead &
- BRW_FS_VARYING_INPUT_MASK) > 16)
+ if (brw->gen < 6 ||
+ _mesa_bitcount_64(fp->program.Base.nir->info.inputs_read &
+ BRW_FS_VARYING_INPUT_MASK) > 16) {
key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
+ }
/* _NEW_COLOR | _NEW_BUFFERS */
@@ -618,9 +620,11 @@ brw_fs_precompile(struct gl_context *ctx,
key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
}
- if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.InputsRead &
- BRW_FS_VARYING_INPUT_MASK) > 16)
- key.input_slots_valid = fp->Base.InputsRead | VARYING_BIT_POS;
+ if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.nir->info.inputs_read &
+ BRW_FS_VARYING_INPUT_MASK) > 16) {
+ key.input_slots_valid =
+ fp->Base.nir->info.inputs_read | VARYING_BIT_POS;
+ }
brw_setup_tex_for_precompile(brw, &key.tex, &fp->Base);
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 059dd90..0ce8a88 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -29,6 +29,7 @@
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_util.h"
+#include "compiler/nir/nir.h"
#include "main/macros.h"
#include "main/fbobject.h"
#include "main/framebuffer.h"
@@ -173,7 +174,8 @@ calculate_attr_overrides(const struct brw_context *brw,
* - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
*/
- bool fs_needs_vue_header = brw->fragment_program->Base.InputsRead &
+ bool fs_needs_vue_header =
+ brw->fragment_program->Base.nir->info.inputs_read &
(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT);
*urb_entry_read_offset = fs_needs_vue_header ? 0 : 1;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 5272217..74e8ddc 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include "compiler/nir/nir.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@@ -92,8 +93,10 @@ upload_sbe(struct brw_context *brw)
/* prepare the active component dwords */
int input_index = 0;
for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
- if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
+ if (!(brw->fragment_program->Base.nir->info.inputs_read &
+ BITFIELD64_BIT(attr))) {
continue;
+ }
assert(input_index < 32);
--
2.7.4
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