[Mesa-dev] [PATCH] gf100/ir: limms on gm107 are 19 bit

[Ilia Mirkin]

Pretty sure that the float one is fine. And there's a 20th bit, it
just behaves differently than one might expect. I don't remember all
the details though...

On Sat, Oct 8, 2016 at 3:23 PM, Karol Herbst <karolherbst at gmail.com> wrote:
> the emit code uses 19 everywhere, so we should let
> CodeEmitterGM107::longIMMD and TargetNVC0::insnCanLoad check against
> this too
>
> Signed-off-by: Karol Herbst <karolherbst at gmail.com>
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp  |  6 +++---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 ++++++++++---
>  2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
> index 3fedafd..fbc2e15 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
> @@ -311,11 +311,11 @@ CodeEmitterGM107::longIMMD(const ValueRef &ref)
>     if (ref.getFile() == FILE_IMMEDIATE) {
>        const ImmediateValue *imm = ref.get()->asImm();
>        if (isFloatType(insn->sType)) {
> -         if ((imm->reg.data.u32 & 0x00000fff) != 0x00000000)
> +         if ((imm->reg.data.u32 & 0x00001fff) != 0x00000000)
>              return true;
>        } else {
> -         if ((imm->reg.data.u32 & 0xfff00000) != 0x00000000 &&
> -             (imm->reg.data.u32 & 0xfff00000) != 0xfff00000)
> +         if ((imm->reg.data.u32 & 0xfff80000) != 0x00000000 &&
> +             (imm->reg.data.u32 & 0xfff80000) != 0xfff80000)
>              return true;
>        }
>     }
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
> index 2d1f1b45..944b072 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
> @@ -356,13 +356,17 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
>                 return false;
>              break;
>           case TYPE_F32:
> -            if (reg.data.u32 & 0xfff)
> +            if (getChipset() < NVISA_GM107_CHIPSET && reg.data.u32 & 0xfff)
> +               return false;
> +            else if (getChipset() >= NVISA_GM107_CHIPSET && reg.data.u32 & 0x1fff)
>                 return false;
>              break;
>           case TYPE_S32:
>           case TYPE_U32:
>              // with u32, 0xfffff counts as 0xffffffff as well
> -            if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
> +            if (getChipset() < NVISA_GM107_CHIPSET && (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000))
> +               return false;
> +            else if (getChipset() >= NVISA_GM107_CHIPSET && (reg.data.s32 > 0x3ffff || reg.data.s32 < -0x40000))
>                 return false;
>              break;
>           case TYPE_U8:
> @@ -378,7 +382,10 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
>        if (i->op == OP_MAD || i->op == OP_FMA) {
>           // requires src == dst, cannot decide before RA
>           // (except if we implement more constraints)
> -         if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
> +         uint32_t data = ld->getSrc(0)->asImm()->reg.data.u32;
> +         if (getChipset() < NVISA_GM107_CHIPSET && (data & 0xfff))
> +            return false;
> +         else if (getChipset() >= NVISA_GM107_CHIPSET && (data & 0x1fff))
>              return false;
>        } else
>        if (i->op == OP_ADD && i->sType == TYPE_F32) {
> --
> 2.10.0
>
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