[Mesa-dev] [PATCH v2 006/103] i965/vec4/nir: set the right type for 64-bit registers

[Iago Toral Quiroga]

From: Connor Abbott <connor.w.abbott at intel.com>

---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 0d4c8f5..05e7f29 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -142,6 +142,9 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
          reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
       unsigned num_regs = array_elems * DIV_ROUND_UP(reg->bit_size, 32);
       nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(num_regs));
+
+      if (reg->bit_size == 64)
+         nir_locals[reg->index].type = BRW_REGISTER_TYPE_DF;
    }
 
    nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);
-- 
2.7.4