[Mesa-dev] [PATCH v2 052/103] i965/vec4: split double-precision bcsel

[Iago Toral Quiroga]

There is a hardware bug affecting compressed double-precision bcsel
instructions in align16 mode by which they won't read predication mask
properly. The bug does not affect other predicated instructions
and it does not affect bcsel in Align1 mode either. This was found
empirically and verified by Curro in the simulator.

Fix this by splitting double-precision bcsel in Align16 mode to use an
execution size of 4.

v2: Check that the dst type is 64-bit, since we can have 16-wide single
    precision bcsel instructions that also write 2 registers.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 69fdb1e..48816be 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1997,6 +1997,12 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
     * only hardware that implements fp64 in Align16.
     */
    if (devinfo->gen == 7 && inst->size_written > REG_SIZE) {
+      /* Align16 8-wide double-precision bcsel does not work well. Verified
+       * empirically.
+       */
+      if (inst->opcode == BRW_OPCODE_SEL && type_sz(inst->dst.type) == 8)
+         lowered_width = MIN2(lowered_width, 4);
+
       /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct
        * Register Addressing:
        *
-- 
2.7.4