[Mesa-dev] [PATCH v2 057/103] i965/vec4: teach register coalescing about 64-bit
Iago Toral Quiroga
itoral at igalia.com
Tue Oct 11 09:02:01 UTC 2016
Specifically, at least for now, we don't want to deal with the fact that
channel sizes for fp64 instructions are twice the size, so prevent
coalescing from instructions with a different type size.
Also, we should check that if we are coalescing a register from another
MOV we should be reading the same amount of data written by that MOV,
Otherwise it might not be safe to eliminate it. This can happen, for example,
when we have split fp64 MOVs with an exec size of 4 that only write one
register each and then a MOV with exec size of 8 that reads both. We want to
avoid the pass to think that it can coalesce from the first split MOV alone.
Ideally we would like the pass to see that it can coalesce from both split
MOVs instead, but for now we keep it simple.
Finally, the pass doesn't support coalescing of multiple registers but in the
case of normal SIMD4x2 double-precision instructions they naturally write two
registers (one per vertex) and there is no reason why we should not allow
coalescing in this case. Change the restriction to bail if we see instructions
that write more than 8 channels, where the channels can be 32-bit or 64-bit.
src/mesa/drivers/dri/i965/brw_vec4.cpp | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c728e38..e5391b9 100644
@@ -1191,6 +1191,19 @@ vec4_visitor::opt_register_coalesce()
scan_inst->dst.type == scan_inst->src.type))
+ /* Only allow coalescing between registers of the same type size.
+ * Otherwise we would need to make the pass aware of the fact that
+ * channel sizes are different for single and double precision.
+ if (type_sz(inst->src.type) != type_sz(scan_inst->src.type))
+ /* Check that scan_inst writes at least the same amount of data
+ * that we read in the instruction
+ if (scan_inst->size_written >= inst->size_read(0))
/* If we can't handle the swizzle, bail. */
if (!scan_inst->can_reswizzle(devinfo, inst->dst.writemask,
@@ -1198,10 +1211,12 @@ vec4_visitor::opt_register_coalesce()
- /* This only handles coalescing of a single register starting at
- * the source offset of the copy instruction.
+ /* This only handles coalescing writes of 8 channels (1 register
+ * for single-precision and 2 registers for double-precision)
+ * starting at the source offset of the copy instruction.
- if (scan_inst->size_written > REG_SIZE ||
+ if (DIV_ROUND_UP(scan_inst->size_written,
+ type_sz(scan_inst->dst.type)) > 8 ||
scan_inst->dst.offset != inst->src.offset)
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