[Mesa-dev] [PATCH 10/26] i965: Provide slice details to renderbuffer fast clear state tracker

Topi Pohjolainen topi.pohjolainen at gmail.com
Tue Oct 11 19:26:42 UTC 2016


This patch also introduces getter and setter for fast clear state
preparing for tracking the state per slice.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.c         |  7 ++--
 src/mesa/drivers/dri/i965/brw_draw.c          | 12 ++++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 +++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 25 ++++++++-------
 4 files changed, 72 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 6332788..83f47aa 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -363,7 +363,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 
    intel_miptree_check_level_layer(src_mt, src_level, src_layer);
    intel_miptree_check_level_layer(dst_mt, dst_level, dst_layer);
-   intel_miptree_used_for_rendering(brw, dst_mt);
+   intel_miptree_used_for_rendering(brw, dst_mt, dst_level,
+                                    dst_logical_layer, 1);
 
    struct isl_surf tmp_surfs[4];
    struct blorp_surf src_surf, dst_surf;
@@ -425,7 +426,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
 
    miptree_check_level_logical_layer(src_mt, src_level, src_layer);
    miptree_check_level_logical_layer(dst_mt, dst_level, dst_layer);
-   intel_miptree_used_for_rendering(brw, dst_mt);
+   intel_miptree_used_for_rendering(brw, dst_mt, dst_level, dst_layer, 1);
 
    struct isl_surf tmp_surfs[4];
    struct blorp_surf src_surf, dst_surf;
@@ -862,7 +863,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
        */
       irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
    } else {
-      intel_miptree_used_for_rendering(brw, irb->mt);
+      intel_miptree_used_for_rendering(brw, irb->mt, level, layer, num_layers);
 
       DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
           irb->mt, irb->mt_level, irb->mt_layer, num_layers);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 5680403..e387eb9 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -386,10 +386,14 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
       struct intel_renderbuffer *irb =
          intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
-      if (irb) {
-         brw_render_cache_set_add_bo(brw, irb->mt->bo);
-         intel_miptree_used_for_rendering(brw, irb->mt);
-      }
+      if (!irb)
+         continue;
+     
+      brw_render_cache_set_add_bo(brw, irb->mt->bo);
+      intel_miptree_used_for_rendering(
+         brw, irb->mt, irb->mt_level,
+         intel_miptree_physical_to_logical_layer(irb->mt, irb->mt_layer),
+         irb->layer_count);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4fb07e9..7b0d411 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2101,6 +2101,13 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 					   BLORP_HIZ_OP_DEPTH_RESOLVE);
 }
 
+enum intel_fast_clear_state
+intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt,
+                                   unsigned level, unsigned layer)
+{
+   return mt->fast_clear_state;
+}
+
 static void
 intel_miptree_check_color_resolve(const struct intel_mipmap_tree *mt,
                                   unsigned level, unsigned layer)
@@ -2122,6 +2129,45 @@ intel_miptree_check_color_resolve(const struct intel_mipmap_tree *mt,
    (void)layer;
 }
 
+void
+intel_miptree_set_fast_clear_state(struct intel_mipmap_tree *mt,
+                                   unsigned level,
+                                   unsigned first_layer,
+                                   unsigned num_layers,
+                                   enum intel_fast_clear_state new_state)
+{
+   intel_miptree_check_color_resolve(mt, level, first_layer);
+
+   assert(first_layer + num_layers <= mt->physical_depth0);
+
+   mt->fast_clear_state = new_state;
+}
+
+void
+intel_miptree_used_for_rendering(const struct brw_context *brw,
+                                 struct intel_mipmap_tree *mt, unsigned level,
+                                 unsigned start_layer, unsigned num_layers)
+{
+   const bool is_lossless_compressed =
+      intel_miptree_is_lossless_compressed(brw, mt);
+
+   for (unsigned i = 0; i < num_layers; ++i) {
+      const enum intel_fast_clear_state fast_clear_state =
+         intel_miptree_get_fast_clear_state(mt, level, start_layer + i);
+
+      /* If the buffer was previously in fast clear state, change it to
+       * unresolved state, since it won't be guaranteed to be clear after
+       * rendering occurs.
+       */
+      if (is_lossless_compressed ||
+          fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR) {
+         intel_miptree_set_fast_clear_state(
+            mt, level, start_layer + i, 1,
+            INTEL_FAST_CLEAR_STATE_UNRESOLVED);
+      }
+   }
+}
+
 bool
 intel_miptree_resolve_color(struct brw_context *brw,
                             struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 57d7b80..44685ca 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -947,22 +947,25 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 
 /**\}*/
 
+enum intel_fast_clear_state
+intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt,
+                                   unsigned level, unsigned layer);
+
+void
+intel_miptree_set_fast_clear_state(struct intel_mipmap_tree *mt,
+                                   unsigned level,
+                                   unsigned first_layer,
+                                   unsigned num_layers,
+                                   enum intel_fast_clear_state new_state);
+
 /**
  * Update the fast clear state for a miptree to indicate that it has been used
  * for rendering.
  */
-static inline void
+void
 intel_miptree_used_for_rendering(const struct brw_context *brw,
-                                 struct intel_mipmap_tree *mt)
-{
-   /* If the buffer was previously in fast clear state, change it to
-    * unresolved state, since it won't be guaranteed to be clear after
-    * rendering occurs.
-    */
-   if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR ||
-      intel_miptree_is_lossless_compressed(brw, mt))
-      mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
-}
+                                 struct intel_mipmap_tree *mt, unsigned level,
+                                 unsigned start_layer, unsigned num_layers);
 
 /**
  * Flag values telling color resolve pass which special types of buffers
-- 
2.5.5



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