[Mesa-dev] [PATCH 2/2] radeonsi: unify the constant load paths

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Thu, Oct 13, 2016 at 3:44 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> Remove the split between direct and indirect.
> ---
>  src/gallium/drivers/radeonsi/si_shader.c | 39 +++++++++-----------------------
>  1 file changed, 11 insertions(+), 28 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
> index 15432b2..34c6eb1 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -1867,66 +1867,49 @@ static LLVMValueRef fetch_constant(
>                 LLVMValueRef values[4];
>                 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
>                         values[chan] = fetch_constant(bld_base, reg, type, chan);
>
>                 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
>         }
>
>         buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
>         idx = reg->Register.Index * 4 + swizzle;
>
> -       if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
> -               LLVMValueRef c0, c1, desc;
> -
> -               desc = load_const_buffer_desc(ctx, buf);
> -               c0 = buffer_load_const(ctx, desc,
> -                                      LLVMConstInt(ctx->i32, idx * 4, 0));
> -
> -               if (!tgsi_type_is_64bit(type))
> -                       return bitcast(bld_base, type, c0);
> -               else {
> -                       c1 = buffer_load_const(ctx, desc,
> -                                              LLVMConstInt(ctx->i32,
> -                                                           (idx + 1) * 4, 0));
> -                       return radeon_llvm_emit_fetch_64bit(bld_base, type,
> -                                                           c0, c1);
> -               }
> -       }
> -
>         if (reg->Register.Dimension && reg->Dimension.Indirect) {
>                 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
>                 LLVMValueRef index;
>                 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
>                                                    reg->Dimension.Index,
>                                                    SI_NUM_CONST_BUFFERS);
>                 bufp = build_indexed_load_const(ctx, ptr, index);
>         } else
>                 bufp = load_const_buffer_desc(ctx, buf);
>
> -       addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
> -       addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
> -       addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
> -       addr = lp_build_add(&bld_base->uint_bld, addr,
> -                           lp_build_const_int32(base->gallivm, idx * 4));
> +       if (reg->Register.Indirect) {
> +               addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
> +               addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
> +               addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
> +               addr = lp_build_add(&bld_base->uint_bld, addr,
> +                                   lp_build_const_int32(base->gallivm, idx * 4));
> +       } else {
> +               addr = LLVMConstInt(ctx->i32, idx * 4, 0);
> +       }
>
>         result = buffer_load_const(ctx, bufp, addr);
>
>         if (!tgsi_type_is_64bit(type))
>                 result = bitcast(bld_base, type, result);
>         else {
>                 LLVMValueRef addr2, result2;
> -               addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
> -               addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
> -               addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
> -               addr2 = lp_build_add(&bld_base->uint_bld, addr2,
> -                                    lp_build_const_int32(base->gallivm, (idx + 1) * 4));
>
> +               addr2 = lp_build_add(&bld_base->uint_bld, addr,
> +                                    LLVMConstInt(ctx->i32, 4, 0));
>                 result2 = buffer_load_const(ctx, bufp, addr2);
>
>                 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
>                                                       result, result2);
>         }
>         return result;
>  }
>
>  /* Upper 16 bits must be zero. */
>  static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
> --
> 2.7.4
>
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