[Mesa-dev] [PATCH] nv50/ir: use levelZero for texgather and non-frag tex/txp ops

[Ilia Mirkin]

On Tue, Oct 18, 2016 at 12:29 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> radeonsi also does the same thing. I suspect that this is likely to be a
> no-op in reality, but it brings nouveau code closer to what the blob
> produces. Plus it makes sense to not try to do auto-derivatives on this.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index e43c951..0e0eecc 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -2193,7 +2193,13 @@ Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
>
>     setTexRS(texi, s, R, S);
>
> -   if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
> +   if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ ||
> +       tgsi.getOpcode() == TGSI_OPCODE_TG4)

Actually I'm dropping this part of the change - the TG4 op doesn't
even have a LZ flag in hw, but some of our emission logic will try to
set bits when it shouldn't. The below hunk is still relevant though.

> +      texi->tex.levelZero = true;
> +   if (prog->getType() != Program::TYPE_FRAGMENT &&
> +       (tgsi.getOpcode() == TGSI_OPCODE_TEX ||
> +        tgsi.getOpcode() == TGSI_OPCODE_TEX2 ||
> +        tgsi.getOpcode() == TGSI_OPCODE_TXP))
>        texi->tex.levelZero = true;
>     if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
>        texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
> --
> 2.7.3
>