[Mesa-dev] [PATCH v2 019/103] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

On 10/11/2016 02:01 AM, Iago Toral Quiroga wrote:
> These align1 opcodes do partial writes of 64-bit data. The problem is that we
> want to use them to write on the same register to implement packDouble2x32 and
> from the point of view of DCE, since both opcodes write to the same register,
> only the last one stands and decides to eliminate the first, which is
> not correct, so prevent this from happening.
> 
> v2: Make a helper in vec4_instruction to know if the instruction is an
>     align1 partial write. This will come in handy when we implement a
>     simd splitting pass in a later patch.
> ---
>  src/mesa/drivers/dri/i965/brw_ir_vec4.h                    | 6 ++++++
>  src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp | 3 ++-
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> index a8e5f4a..7451f44 100644
> --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> @@ -232,6 +232,12 @@ public:
>     bool can_change_types() const;
>     bool has_source_and_destination_hazard() const;
>  
> +   bool is_align1_partial_write()
> +   {
> +      return opcode == VEC4_OPCODE_SET_LOW_32BIT ||
> +             opcode == VEC4_OPCODE_SET_HIGH_32BIT;
> +   }
> +
>     bool reads_flag()
>     {
>        return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> index 50706a9..950c6c8 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> @@ -109,7 +109,8 @@ vec4_visitor::dead_code_eliminate()
>              }
>           }
>  
> -         if (inst->dst.file == VGRF && !inst->predicate) {
> +         if (inst->dst.file == VGRF && !inst->predicate &&
> +             !inst->is_align1_partial_write()) {
>              for (unsigned i = 0; i < regs_written(inst); i++) {
>                 for (int c = 0; c < 4; c++) {
>                    if (inst->dst.writemask & (1 << c)) {
>