[Mesa-dev] [PATCH 35/42] i965/mesa/st/swrast: set fs shader_info directly and switch to using it
Timothy Arceri
timothy.arceri at collabora.com
Wed Oct 19 23:09:52 UTC 2016
Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.
---
src/compiler/glsl/ir_set_program_inouts.cpp | 14 ++++----------
src/compiler/shader_info.c | 3 ---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/brw_curbe.c | 3 +--
src/mesa/drivers/dri/i965/brw_sf.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm.c | 22 +++++++++-------------
src/mesa/drivers/dri/i965/brw_wm_state.c | 8 ++++----
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +--
src/mesa/drivers/dri/i965/gen6_sf_state.c | 3 +--
src/mesa/drivers/dri/i965/gen8_sf_state.c | 2 +-
src/mesa/main/shaderapi.c | 3 +--
src/mesa/program/arbprogparse.c | 2 +-
src/mesa/program/ir_to_mesa.cpp | 3 +--
src/mesa/program/prog_to_nir.c | 6 ------
src/mesa/program/program.c | 2 +-
src/mesa/state_tracker/st_program.c | 4 ++--
src/mesa/swrast/s_context.c | 2 +-
17 files changed, 30 insertions(+), 54 deletions(-)
diff --git a/src/compiler/glsl/ir_set_program_inouts.cpp b/src/compiler/glsl/ir_set_program_inouts.cpp
index a177219..e68ecfb 100644
--- a/src/compiler/glsl/ir_set_program_inouts.cpp
+++ b/src/compiler/glsl/ir_set_program_inouts.cpp
@@ -26,8 +26,6 @@
*
* Sets the InputsRead and OutputsWritten of Mesa programs.
*
- * Additionally, for fragment shaders, set the IsSample bitfield.
- *
* Mesa programs (gl_program, not gl_shader_program) have a set of
* flags indicating which varyings are read and written. Computing
* which are actually read from some sort of backend code can be
@@ -123,9 +121,7 @@ mark(struct gl_program *prog, ir_variable *var, int offset, int len,
prog->DoubleInputsRead |= bitfield;
if (stage == MESA_SHADER_FRAGMENT) {
- gl_fragment_program *fprog = (gl_fragment_program *) prog;
- if (var->data.sample)
- fprog->IsSample |= bitfield;
+ prog->info.fs.uses_sample_qualifier |= var->data.sample;
}
} else if (var->data.mode == ir_var_system_value) {
prog->SystemValuesRead |= bitfield;
@@ -411,8 +407,7 @@ ir_set_program_inouts_visitor::visit_enter(ir_discard *)
/* discards are only allowed in fragment shaders. */
assert(this->shader_stage == MESA_SHADER_FRAGMENT);
- gl_fragment_program *fprog = (gl_fragment_program *) prog;
- fprog->UsesKill = true;
+ prog->info.fs.uses_discard = true;
return visit_continue;
}
@@ -439,9 +434,8 @@ do_set_program_inouts(exec_list *instructions, struct gl_program *prog,
prog->PatchOutputsWritten = 0;
prog->SystemValuesRead = 0;
if (shader_stage == MESA_SHADER_FRAGMENT) {
- gl_fragment_program *fprog = (gl_fragment_program *) prog;
- fprog->IsSample = 0;
- fprog->UsesKill = false;
+ prog->info.fs.uses_sample_qualifier = false;
+ prog->info.fs.uses_discard = false;
}
visit_list_elements(&v, instructions);
}
diff --git a/src/compiler/shader_info.c b/src/compiler/shader_info.c
index 9329e51..7118e79 100644
--- a/src/compiler/shader_info.c
+++ b/src/compiler/shader_info.c
@@ -44,10 +44,7 @@ copy_shader_info(const struct gl_shader_program *shader_prog,
struct gl_fragment_program *fp =
(struct gl_fragment_program *)sh->Program;
- info->fs.uses_discard = fp->UsesKill;
- info->fs.uses_sample_qualifier = fp->IsSample != 0;
info->fs.early_fragment_tests = sh->info.EarlyFragmentTests;
- info->fs.depth_layout = fp->FragDepthLayout;
break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 68f0073..2048bea 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -305,7 +305,7 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
/* Resolve color buffers for non-coherent framebuffer fetch. */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
ctx->FragmentProgram._Current &&
- ctx->FragmentProgram._Current->Base.nir->info->outputs_read) {
+ ctx->FragmentProgram._Current->Base.info.outputs_read) {
const struct gl_framebuffer *fb = ctx->DrawBuffer;
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index f3f5a80..0e94d15 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -325,8 +325,7 @@ emit:
* BRW_NEW_FRAGMENT_PROGRAM
*/
if (brw->gen == 4 && !brw->is_g4x &&
- (brw->fragment_program->Base.nir->info->inputs_read &
- (1 << VARYING_SLOT_POS))) {
+ (brw->fragment_program->Base.info.inputs_read & (1 << VARYING_SLOT_POS))) {
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index 308b056..1fd3bac 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -191,7 +191,7 @@ brw_upload_sf_prog(struct brw_context *brw)
if (key.do_point_sprite) {
key.point_sprite_coord_replace = ctx->Point.CoordReplace & 0xff;
}
- if (brw->fragment_program->Base.nir->info->inputs_read &
+ if (brw->fragment_program->Base.info.inputs_read &
BITFIELD64_BIT(VARYING_SLOT_PNTC)) {
key.do_point_coord = 1;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 53b7d9b..ce81525 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -450,13 +450,11 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
*/
if (brw->gen < 6) {
/* _NEW_COLOR */
- if (fp->program.Base.nir->info->fs.uses_discard ||
- ctx->Color.AlphaEnabled) {
+ if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) {
lookup |= IZ_PS_KILL_ALPHATEST_BIT;
}
- if (fp->program.Base.nir->info->outputs_written &
- BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+ if (prog->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
}
@@ -545,9 +543,8 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
}
/* BRW_NEW_VUE_MAP_GEOM_OUT */
- if (brw->gen < 6 ||
- _mesa_bitcount_64(fp->program.Base.nir->info->inputs_read &
- BRW_FS_VARYING_INPUT_MASK) > 16) {
+ if (brw->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
+ BRW_FS_VARYING_INPUT_MASK) > 16) {
key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
}
@@ -609,10 +606,10 @@ brw_fs_precompile(struct gl_context *ctx,
memset(&key, 0, sizeof(key));
- uint64_t outputs_written = fp->Base.nir->info->outputs_written;
+ uint64_t outputs_written = prog->info.outputs_written;
if (brw->gen < 6) {
- if (fp->Base.nir->info->fs.uses_discard)
+ if (prog->info.fs.uses_discard)
key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
if (outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
@@ -623,10 +620,9 @@ brw_fs_precompile(struct gl_context *ctx,
key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
}
- if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.nir->info->inputs_read &
+ if (brw->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
BRW_FS_VARYING_INPUT_MASK) > 16) {
- key.input_slots_valid =
- fp->Base.nir->info->inputs_read | VARYING_BIT_POS;
+ key.input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS;
}
brw_setup_tex_for_precompile(brw, &key.tex, &fp->Base);
@@ -647,7 +643,7 @@ brw_fs_precompile(struct gl_context *ctx,
struct brw_vue_map vue_map;
if (brw->gen < 6) {
brw_compute_vue_map(&brw->screen->devinfo, &vue_map,
- fp->Base.nir->info->inputs_read | VARYING_BIT_POS,
+ prog->info.inputs_read | VARYING_BIT_POS,
false);
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ad5e233..8808ac1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -48,13 +48,13 @@ brw_color_buffer_write_enabled(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FRAGMENT_PROGRAM */
- const struct gl_fragment_program *fp = brw->fragment_program;
+ const struct gl_program *fp = &brw->fragment_program->Base;
unsigned i;
/* _NEW_BUFFERS */
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
- uint64_t outputs_written = fp->Base.nir->info->outputs_written;
+ uint64_t outputs_written = fp->info.outputs_written;
/* _NEW_COLOR */
if (rb && (outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
@@ -79,7 +79,7 @@ brw_upload_wm_unit(struct brw_context *brw)
const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FRAGMENT_PROGRAM */
- const struct gl_fragment_program *fp = brw->fragment_program;
+ const struct gl_program *fp = &brw->fragment_program->Base;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
@@ -168,7 +168,7 @@ brw_upload_wm_unit(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
wm->wm5.program_uses_depth = prog_data->uses_src_depth;
- wm->wm5.program_computes_depth = (fp->Base.nir->info->outputs_written &
+ wm->wm5.program_computes_depth = (fp->info.outputs_written &
BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
/* _NEW_BUFFERS
* Override for NULL depthbuffer case, required by the Pixel Shader Computed
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d2cbf50..b64f122 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1146,8 +1146,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
- brw->fragment_program &&
- brw->fragment_program->Base.nir->info->outputs_read) {
+ brw->fragment_program && brw->fragment_program->Base.info.outputs_read) {
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 3824e6e..bb24989 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -177,8 +177,7 @@ calculate_attr_overrides(const struct brw_context *brw,
* - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
*/
- bool fs_needs_vue_header =
- brw->fragment_program->Base.nir->info->inputs_read &
+ bool fs_needs_vue_header = brw->fragment_program->Base.info.inputs_read &
(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT);
*urb_entry_read_offset = fs_needs_vue_header ? 0 : 1;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 528d835..107c02b 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -95,7 +95,7 @@ upload_sbe(struct brw_context *brw)
/* prepare the active component dwords */
int input_index = 0;
for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
- if (!(brw->fragment_program->Base.nir->info->inputs_read &
+ if (!(brw->fragment_program->Base.info.inputs_read &
BITFIELD64_BIT(attr))) {
continue;
}
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index bcf53bb..4996e8e 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -2196,8 +2196,7 @@ _mesa_copy_linked_program_data(const struct gl_shader_program *src,
break;
}
case MESA_SHADER_FRAGMENT: {
- struct gl_fragment_program *dst_fp = (struct gl_fragment_program *) dst;
- dst_fp->FragDepthLayout = src->FragDepthLayout;
+ dst->info.fs.depth_layout = src->FragDepthLayout;
break;
}
case MESA_SHADER_COMPUTE: {
diff --git a/src/mesa/program/arbprogparse.c b/src/mesa/program/arbprogparse.c
index 80a0528..82bdd13 100644
--- a/src/mesa/program/arbprogparse.c
+++ b/src/mesa/program/arbprogparse.c
@@ -119,7 +119,7 @@ _mesa_parse_arb_fragment_program(struct gl_context* ctx, GLenum target,
program->OriginUpperLeft = state.option.OriginUpperLeft;
program->PixelCenterInteger = state.option.PixelCenterInteger;
- program->UsesKill = state.fragment.UsesKill;
+ program->Base.info.fs.uses_discard = state.fragment.UsesKill;
free(program->Base.Instructions);
program->Base.Instructions = prog.Instructions;
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 00ee3e3..03af116 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -2926,8 +2926,7 @@ get_mesa_program(struct gl_context *ctx,
/* Set the gl_FragDepth layout. */
if (target == GL_FRAGMENT_PROGRAM_ARB) {
- struct gl_fragment_program *fp = (struct gl_fragment_program *)prog;
- fp->FragDepthLayout = shader_program->FragDepthLayout;
+ prog->info.fs.depth_layout = shader_program->FragDepthLayout;
}
_mesa_reference_program(ctx, &shader->Program, prog);
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 1192207..fb34b3c 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -1061,12 +1061,6 @@ prog_to_nir(const struct gl_program *prog,
s->info->uses_clip_distance_out = false;
s->info->separate_shader = false;
- if (stage == MESA_SHADER_FRAGMENT) {
- struct gl_fragment_program *fp = (struct gl_fragment_program *)prog;
-
- s->info->fs.uses_discard = fp->UsesKill;
- }
-
fail:
if (c->error) {
ralloc_free(s);
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index 61cc6fe..1d9eaa0 100644
--- a/src/mesa/program/program.c
+++ b/src/mesa/program/program.c
@@ -521,7 +521,7 @@ _mesa_get_min_invocations_per_fragment(struct gl_context *ctx,
* "Use of the "sample" qualifier on a fragment shader input
* forces per-sample shading"
*/
- if (prog->IsSample && !ignore_sample_qualifier)
+ if (prog->Base.info.fs.uses_sample_qualifier && !ignore_sample_qualifier)
return MAX2(_mesa_geometric_samples(ctx->DrawBuffer), 1);
if (prog->Base.SystemValuesRead & (SYSTEM_BIT_SAMPLE_ID |
diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c
index 7a4ac26..31cfbca 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -844,8 +844,8 @@ st_translate_fragment_program(struct st_context *st,
if (write_all == GL_TRUE)
ureg_property(ureg, TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 1);
- if (stfp->Base.FragDepthLayout != FRAG_DEPTH_LAYOUT_NONE) {
- switch (stfp->Base.FragDepthLayout) {
+ if (stfp->Base.Base.info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
+ switch (stfp->Base.Base.info.fs.depth_layout) {
case FRAG_DEPTH_LAYOUT_ANY:
ureg_property(ureg, TGSI_PROPERTY_FS_DEPTH_LAYOUT,
TGSI_FS_DEPTH_LAYOUT_ANY);
diff --git a/src/mesa/swrast/s_context.c b/src/mesa/swrast/s_context.c
index a63179c..325a0a8 100644
--- a/src/mesa/swrast/s_context.c
+++ b/src/mesa/swrast/s_context.c
@@ -226,7 +226,7 @@ _swrast_update_deferred_texture(struct gl_context *ctx)
/* Z comes from fragment program/shader */
swrast->_DeferredTexture = GL_FALSE;
}
- else if (use_fprog && fprog->UsesKill) {
+ else if (use_fprog && fprog->Base.info.fs.uses_discard) {
swrast->_DeferredTexture = GL_FALSE;
}
else if (ctx->Query.CurrentOcclusionObject) {
--
2.7.4
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