[Mesa-dev] [PATCH 20/42] i965: switch vs over to shared shader_info

[Timothy Arceri]

Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.
---
 src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
 src/mesa/drivers/dri/i965/brw_vs.c   | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index a2e0442..92a500c 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -302,7 +302,7 @@ brw_merge_inputs(struct brw_context *brw,
    }
 
    if (brw->gen < 8 && !brw->is_haswell) {
-      uint64_t mask = ctx->VertexProgram._Current->Base.nir->info->inputs_read;
+      uint64_t mask = ctx->VertexProgram._Current->Base.info.inputs_read;
       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
        */
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index f24a2ee..a7f89f3 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -150,9 +150,8 @@ brw_codegen_vs_prog(struct brw_context *brw,
    }
 
    uint64_t outputs_written =
-      brw_vs_outputs_written(brw, key,
-                             vp->program.Base.nir->info->outputs_written);
-   prog_data.inputs_read = vp->program.Base.nir->info->inputs_read;
+      brw_vs_outputs_written(brw, key, vp->program.Base.info.outputs_written);
+   prog_data.inputs_read = vp->program.Base.info.inputs_read;
 
    if (key->copy_edgeflag) {
       prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
-- 
2.7.4