[Mesa-dev] [PATCH v2] intel: genxml: add SO_WRITE_OFFSET register

[Lionel Landwerlin]

One of the register we happen to program but don't have a description for
yet.

v2: Add SO_WRITE_OFFSET[1-3] on gen7+ (Kenneth)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 src/intel/genxml/gen6.xml  |  5 +++++
 src/intel/genxml/gen7.xml  | 20 ++++++++++++++++++++
 src/intel/genxml/gen75.xml | 20 ++++++++++++++++++++
 src/intel/genxml/gen8.xml  | 20 ++++++++++++++++++++
 src/intel/genxml/gen9.xml  | 20 ++++++++++++++++++++
 5 files changed, 85 insertions(+)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 7ba8954..b907710 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1995,4 +1995,9 @@
     <field name="System Instruction Pointer" start="36" end="63" type="offset"/>
   </instruction>

+  <register name="SO_WRITE_OFFSET" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
 </genxml>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index a950603..c147f04 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2528,6 +2528,26 @@
     <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>

+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528C">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3SQCREG1" length="1" num="0xb010">
     <field name="Convert DC_UC" start="24" end="24" type="uint"/>
     <field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 2c522d5..df2316c 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2936,6 +2936,26 @@
     <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>

+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528C">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3SQCREG1" length="1" num="0xb010">
     <field name="Convert DC_UC" start="24" end="24" type="uint"/>
     <field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 73c9265..10bb8f3 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3167,6 +3167,26 @@
     <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>

+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528C">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3CNTLREG" length="1" num="0x7034">
     <field name="SLM Enable" start="0" end="0" type="uint"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 0dfce3f..9dd9197 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3441,6 +3441,26 @@
     <field name="System Instruction Pointer" start="36" end="95" type="offset"/>
   </instruction>

+  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
+  <register name="SO_WRITE_OFFSET3" length="1" num="0x528C">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3CNTLREG" length="1" num="0x7034">
     <field name="SLM Enable" start="0" end="0" type="uint"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
--
2.9.3