[Mesa-dev] [PATCH 14/24] gallium/radeon: remove flags specific to libdrm_radeon from winsys interface

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

These just say whether libdrm can assume that the latest radeon_surface
definition is used by Mesa.
---
 src/gallium/drivers/radeon/r600_texture.c          | 14 ++------------
 src/gallium/drivers/radeon/radeon_winsys.h         |  3 +--
 src/gallium/winsys/radeon/drm/radeon_drm_surface.c |  4 +++-
 3 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 4d4be97..dcfa7cd 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -226,28 +226,22 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 		if (tc_compatible_htile &&
 		    array_mode == RADEON_SURF_MODE_2D) {
 			/* TC-compatible HTILE only supports Z32_FLOAT.
 			 * Promote Z16 to Z32. DB->CB copies will convert
 			 * the format for transfers.
 			 */
 			bpe = 4;
 			flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
 		}
 
-		if (is_stencil) {
-			flags |= RADEON_SURF_SBUFFER |
-				 RADEON_SURF_HAS_SBUFFER_MIPTREE;
-		}
-	}
-
-	if (rscreen->chip_class >= SI) {
-		flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+		if (is_stencil)
+			flags |= RADEON_SURF_SBUFFER;
 	}
 
 	if (rscreen->chip_class >= VI &&
 	    (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
 	     ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
 		flags |= RADEON_SURF_DISABLE_DCC;
 
 	if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
 		/* This should catch bugs in gallium users setting incorrect flags. */
 		assert(ptex->nr_samples <= 1 &&
@@ -598,24 +592,20 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 
 	templ.nr_samples = 1;
 	flags = rtex->surface.flags | RADEON_SURF_FMASK;
 
 	/* Use the same parameters and tile mode. */
 	fmask.bankw = rtex->surface.bankw;
 	fmask.bankh = rtex->surface.bankh;
 	fmask.mtilea = rtex->surface.mtilea;
 	fmask.tile_split = rtex->surface.tile_split;
 
-	if (rscreen->chip_class >= SI) {
-		flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-	}
-
 	switch (nr_samples) {
 	case 2:
 	case 4:
 		bpe = 1;
 		if (rscreen->chip_class <= CAYMAN) {
 			fmask.bankh = 4;
 		}
 		break;
 	case 8:
 		bpe = 4;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index bf4bb82..29b64c0 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -261,22 +261,21 @@ enum radeon_surf_mode {
     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
     RADEON_SURF_MODE_1D = 2,
     RADEON_SURF_MODE_2D = 3,
 };
 
 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_SCANOUT                     (1 << 16)
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
-#define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
-#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
+/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 
 struct radeon_surf_level {
     uint64_t                    offset;
     uint64_t                    slice_size;
     uint64_t                    dcc_offset;
     uint64_t                    dcc_fast_clear_size;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index ed61406..e35f8a4 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -105,21 +105,23 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
     surf_drm->blk_h = util_format_get_blockheight(tex->format);
     surf_drm->blk_d = 1;
     surf_drm->array_size = 1;
     surf_drm->last_level = tex->last_level;
     surf_drm->bpe = bpe;
     surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
 
     surf_drm->flags = flags;
     surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
     surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
-    surf_drm->flags |= RADEON_SURF_SET(mode, MODE);
+    surf_drm->flags |= RADEON_SURF_SET(mode, MODE) |
+                       RADEON_SURF_HAS_SBUFFER_MIPTREE |
+                       RADEON_SURF_HAS_TILE_MODE_INDEX;
 
     switch (tex->target) {
     case PIPE_TEXTURE_1D:
             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
             break;
     case PIPE_TEXTURE_RECT:
     case PIPE_TEXTURE_2D:
             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
             break;
     case PIPE_TEXTURE_3D:
-- 
2.7.4