[Mesa-dev] [PATCH 03/24] gallium/radeon: use r600_gfx_write_event_eop everywhere

[Nicolai Hähnle]

On 25.10.2016 00:33, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
>  src/gallium/drivers/radeon/r600_pipe_common.c |  4 +++-
>  src/gallium/drivers/radeon/r600_query.c       | 17 ++++-------------
>  src/gallium/drivers/radeonsi/si_state_draw.c  | 12 +++---------
>  3 files changed, 10 insertions(+), 23 deletions(-)
>
[snip]
> diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
> index ac71a43..a5c8595 100644
> --- a/src/gallium/drivers/radeon/r600_query.c
> +++ b/src/gallium/drivers/radeon/r600_query.c
> @@ -550,26 +550,22 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
>  	case PIPE_QUERY_PRIMITIVES_EMITTED:
>  	case PIPE_QUERY_PRIMITIVES_GENERATED:
>  	case PIPE_QUERY_SO_STATISTICS:
>  	case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>  		radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
>  		radeon_emit(cs, va);
>  		radeon_emit(cs, (va >> 32) & 0xFFFF);
>  		break;
>  	case PIPE_QUERY_TIME_ELAPSED:
> -		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
> -		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
> -		radeon_emit(cs, va);
> -		radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
> -		radeon_emit(cs, 0);
> -		radeon_emit(cs, 0);
> +		r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
> +					 0, 3, NULL, va, 0, 0);

I haven't been particularly fond of having the r600_emit_reloc below the 
switch in this function even though I may have been the one who put it 
there in the first place. Especially with this change, I think it'd 
benefit from being moved up to the cases where it's still needed (and 
passing the buf to r600_gfx_write_event_eop in this case here).

Apart from that, patches 1&2:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>


>  		break;
>  	case PIPE_QUERY_PIPELINE_STATISTICS:
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>  		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
>  		radeon_emit(cs, va);
>  		radeon_emit(cs, (va >> 32) & 0xFFFF);
>  		break;
>  	default:
>  		assert(0);
>  	}
> @@ -636,27 +632,22 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
>  		va += query->result_size/2;
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>  		radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
>  		radeon_emit(cs, va);
>  		radeon_emit(cs, (va >> 32) & 0xFFFF);
>  		break;
>  	case PIPE_QUERY_TIME_ELAPSED:
>  		va += 8;
>  		/* fall through */
>  	case PIPE_QUERY_TIMESTAMP:
> -		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
> -		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
> -		radeon_emit(cs, va);
> -		radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
> -		radeon_emit(cs, 0);
> -		radeon_emit(cs, 0);
> -
> +		r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
> +					 0, 3, NULL, va, 0, 0);
>  		fence_va = va + 8;
>  		break;
>  	case PIPE_QUERY_PIPELINE_STATISTICS: {
>  		unsigned sample_size = (query->result_size - 8) / 2;
>
>  		va += sample_size;
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>  		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
>  		radeon_emit(cs, va);
>  		radeon_emit(cs, (va >> 32) & 0xFFFF);
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index d18137b..c0e2642 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -733,29 +733,23 @@ void si_emit_cache_flush(struct si_context *sctx)
>  				 S_0085F0_CB0_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB1_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB2_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB3_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB4_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB5_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB6_DEST_BASE_ENA(1) |
>  			         S_0085F0_CB7_DEST_BASE_ENA(1);
>
>  		/* Necessary for DCC */
> -		if (rctx->chip_class >= VI) {
> -			radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
> -			radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
> -			                EVENT_INDEX(5));
> -			radeon_emit(cs, 0);
> -			radeon_emit(cs, 0);
> -			radeon_emit(cs, 0);
> -			radeon_emit(cs, 0);
> -		}
> +		if (rctx->chip_class == VI)
> +			r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
> +						 0, 0, NULL, 0, 0, 0);
>  	}
>  	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
>  		cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
>  				 S_0085F0_DB_DEST_BASE_ENA(1);
>  	}
>
>  	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
>  		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
>  		/* needed for wait for idle in SURFACE_SYNC */
>