[Mesa-dev] [PATCH 3/5] i965: get num_images from shader_info rather than gl_linked_shader
Timothy Arceri
timothy.arceri at collabora.com
Thu Oct 27 09:01:55 UTC 2016
This is a step towards freeing gl_linked_shader after linking.
---
src/mesa/drivers/dri/i965/brw_context.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_cs.c | 5 +++--
src/mesa/drivers/dri/i965/brw_gs.c | 5 +++--
src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 5 +++--
src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_tcs.c | 11 ++++++-----
src/mesa/drivers/dri/i965/brw_tcs_surface_state.c | 5 +++--
src/mesa/drivers/dri/i965/brw_tes.c | 9 +++++----
src/mesa/drivers/dri/i965/brw_tes_surface_state.c | 5 +++--
src/mesa/drivers/dri/i965/brw_vs.c | 3 +--
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 5 +++--
src/mesa/drivers/dri/i965/brw_wm.c | 3 +--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 ++++++++++------
14 files changed, 46 insertions(+), 35 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index af8ed2c..1f95bf0 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -275,8 +275,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
ctx->_Shader->CurrentProgram[i] ?
ctx->_Shader->CurrentProgram[i]->_LinkedShaders[i] : NULL;
- if (unlikely(shader && shader->NumImages)) {
- for (unsigned j = 0; j < shader->NumImages; j++) {
+ if (unlikely(shader && shader->Program->info.num_images)) {
+ for (unsigned j = 0; j < shader->Program->info.num_images; j++) {
struct gl_image_unit *u = &ctx->ImageUnits[shader->ImageUnits[j]];
tex_obj = intel_texture_object(u->TexObj);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 5c64c2f..a874941 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1515,6 +1515,7 @@ void brw_upload_abo_surfaces(struct brw_context *brw,
struct brw_stage_prog_data *prog_data);
void brw_upload_image_surfaces(struct brw_context *brw,
struct gl_linked_shader *shader,
+ const struct gl_program *prog,
struct brw_stage_state *stage_state,
struct brw_stage_prog_data *prog_data);
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index d16fff8..9a90464 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -103,9 +103,10 @@ brw_codegen_cs_prog(struct brw_context *brw,
prog_data.base.pull_param =
rzalloc_array(NULL, const gl_constant_value *, param_count);
prog_data.base.image_param =
- rzalloc_array(NULL, struct brw_image_param, cs->base.NumImages);
+ rzalloc_array(NULL, struct brw_image_param,
+ cp->program.info.num_images);
prog_data.base.nr_params = param_count;
- prog_data.base.nr_image_params = cs->base.NumImages;
+ prog_data.base.nr_image_params = cp->program.info.num_images;
brw_nir_setup_glsl_uniforms(cp->program.nir, prog, &cp->program,
&prog_data.base, true);
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 0f052d2..7cd272c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -125,9 +125,10 @@ brw_codegen_gs_prog(struct brw_context *brw,
prog_data.base.base.pull_param =
rzalloc_array(NULL, const gl_constant_value *, param_count);
prog_data.base.base.image_param =
- rzalloc_array(NULL, struct brw_image_param, gs->NumImages);
+ rzalloc_array(NULL, struct brw_image_param,
+ gp->program.info.num_images);
prog_data.base.base.nr_params = param_count;
- prog_data.base.base.nr_image_params = gs->NumImages;
+ prog_data.base.base.nr_image_params = gp->program.info.num_images;
brw_nir_setup_glsl_uniforms(gp->program.nir, prog, &gp->program,
&prog_data.base.base,
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
index 4d0f50c..dd43edf 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -129,11 +129,12 @@ brw_upload_gs_image_surfaces(struct brw_context *brw)
/* BRW_NEW_GEOMETRY_PROGRAM */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_GEOMETRY];
+ const struct gl_program *gp = brw->geometry_program;
- if (prog) {
+ if (gp && prog) {
/* BRW_NEW_GS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
- &brw->gs.base, brw->gs.base.prog_data);
+ gp, &brw->gs.base, brw->gs.base.prog_data);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61bc868..db79718 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1231,9 +1231,9 @@ brw_assign_common_binding_table_offsets(gl_shader_stage stage,
stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
}
- if (shader && shader->NumImages) {
+ if (prog->info.num_images) {
stage_prog_data->binding_table.image_start = next_binding_table_offset;
- next_binding_table_offset += shader->NumImages;
+ next_binding_table_offset += prog->info.num_images;
} else {
stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 58d080d..c8f0c4d 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -199,8 +199,6 @@ brw_codegen_tcs_prog(struct brw_context *brw,
* padding around uniform values below vec4 size, so the worst case is that
* every uniform is a float which gets padded to the size of a vec4.
*/
- struct gl_linked_shader *tcs = shader_prog ?
- shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;
int param_count = nir->num_uniforms / 4;
prog_data.base.base.param =
@@ -209,14 +207,15 @@ brw_codegen_tcs_prog(struct brw_context *brw,
rzalloc_array(NULL, const gl_constant_value *, param_count);
prog_data.base.base.nr_params = param_count;
- if (tcs) {
+ if (tcp) {
brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo,
shader_prog, &tcp->program,
&prog_data.base.base, 0);
prog_data.base.base.image_param =
- rzalloc_array(NULL, struct brw_image_param, tcs->NumImages);
- prog_data.base.base.nr_image_params = tcs->NumImages;
+ rzalloc_array(NULL, struct brw_image_param,
+ tcp->program.info.num_images);
+ prog_data.base.base.nr_image_params = tcp->program.info.num_images;
brw_nir_setup_glsl_uniforms(nir, shader_prog, &tcp->program,
&prog_data.base.base,
@@ -248,6 +247,8 @@ brw_codegen_tcs_prog(struct brw_context *brw,
}
}
+ struct gl_linked_shader *tcs = shader_prog ?
+ shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;
if (unlikely(INTEL_DEBUG & DEBUG_TCS) && tcs)
brw_dump_ir("tessellation control", shader_prog, tcs, NULL);
diff --git a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
index 83b5611..06bdfa3 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
@@ -129,11 +129,12 @@ brw_upload_tcs_image_surfaces(struct brw_context *brw)
/* BRW_NEW_TESS_PROGRAMS */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
+ const struct gl_program *tcp = brw->tess_ctrl_program;
- if (prog) {
+ if (tcp && prog) {
/* BRW_NEW_TCS_PROG_DATA, BRW_NEW_IMAGE_UNITS */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
- &brw->tcs.base, brw->tcs.base.prog_data);
+ tcp, &brw->tcs.base, brw->tcs.base.prog_data);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 6060c76..e322159 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -150,8 +150,6 @@ brw_codegen_tes_prog(struct brw_context *brw,
* padding around uniform values below vec4 size, so the worst case is that
* every uniform is a float which gets padded to the size of a vec4.
*/
- struct gl_linked_shader *tes =
- shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
int param_count = nir->num_uniforms / 4;
prog_data.base.base.param =
@@ -159,9 +157,10 @@ brw_codegen_tes_prog(struct brw_context *brw,
prog_data.base.base.pull_param =
rzalloc_array(NULL, const gl_constant_value *, param_count);
prog_data.base.base.image_param =
- rzalloc_array(NULL, struct brw_image_param, tes->NumImages);
+ rzalloc_array(NULL, struct brw_image_param,
+ tep->program.info.num_images);
prog_data.base.base.nr_params = param_count;
- prog_data.base.base.nr_image_params = tes->NumImages;
+ prog_data.base.base.nr_image_params = tep->program.info.num_images;
prog_data.base.cull_distance_mask =
((1 << tep->program.CullDistanceArraySize) - 1) <<
@@ -171,6 +170,8 @@ brw_codegen_tes_prog(struct brw_context *brw,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
+ struct gl_linked_shader *tes =
+ shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
if (unlikely(INTEL_DEBUG & DEBUG_TES))
brw_dump_ir("tessellation evaluation", shader_prog, tes, NULL);
diff --git a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
index 53b39cd..1b31b20 100644
--- a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
@@ -129,11 +129,12 @@ brw_upload_tes_image_surfaces(struct brw_context *brw)
/* BRW_NEW_TESS_PROGRAMS */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
+ const struct gl_program *tep = brw->tess_eval_program;
- if (prog) {
+ if (tep && prog) {
/* BRW_NEW_TES_PROG_DATA, BRW_NEW_IMAGE_UNITS */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_EVAL],
- &brw->tes.base, brw->tes.base.prog_data);
+ tep, &brw->tes.base, brw->tes.base.prog_data);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 842c516..bd11b8f 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -122,8 +122,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
*/
int param_count = vp->program.nir->num_uniforms / 4;
- if (vs)
- prog_data.base.base.nr_image_params = vs->base.NumImages;
+ prog_data.base.base.nr_image_params = vp->program.info.num_images;
/* vec4_visitor::setup_uniform_clipplane_values() also uploads user clip
* planes as uniforms.
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 6a97cd4..891fd5d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -195,11 +195,12 @@ brw_upload_vs_image_surfaces(struct brw_context *brw)
/* BRW_NEW_VERTEX_PROGRAM */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX];
+ const struct gl_program *vp = brw->vertex_program;
- if (prog) {
+ if (vp && prog) {
/* BRW_NEW_VS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX],
- &brw->vs.base, brw->vs.base.prog_data);
+ vp, &brw->vs.base, brw->vs.base.prog_data);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index f433ed6..4c70803 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -107,8 +107,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
* by the state cache.
*/
int param_count = fp->program.nir->num_uniforms / 4;
- if (fs)
- prog_data.base.nr_image_params = fs->base.NumImages;
+ prog_data.base.nr_image_params = fp->program.info.num_images;
/* The backend also sometimes adds params for texture size. */
param_count += 2 * ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits;
prog_data.base.param =
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index fcd753c..db3b4e2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1565,11 +1565,12 @@ brw_upload_cs_image_surfaces(struct brw_context *brw)
/* _NEW_PROGRAM */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+ const struct gl_program *cp = brw->compute_program;
- if (prog) {
+ if (cp && prog) {
/* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
- &brw->cs.base, brw->cs.base.prog_data);
+ cp, &brw->cs.base, brw->cs.base.prog_data);
}
}
@@ -1776,13 +1777,15 @@ update_image_surface(struct brw_context *brw,
void
brw_upload_image_surfaces(struct brw_context *brw,
struct gl_linked_shader *shader,
+ const struct gl_program *prog,
struct brw_stage_state *stage_state,
struct brw_stage_prog_data *prog_data)
{
+ assert(prog);
struct gl_context *ctx = &brw->ctx;
- if (shader && shader->NumImages) {
- for (unsigned i = 0; i < shader->NumImages; i++) {
+ if (prog->info.num_images && shader) {
+ for (unsigned i = 0; i < prog->info.num_images; i++) {
struct gl_image_unit *u = &ctx->ImageUnits[shader->ImageUnits[i]];
const unsigned surf_idx = prog_data->binding_table.image_start + i;
@@ -1807,11 +1810,12 @@ brw_upload_wm_image_surfaces(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FRAGMENT_PROGRAM */
struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
+ const struct gl_program *wm = brw->fragment_program;
- if (prog) {
+ if (wm && prog) {
/* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, brw->wm.base.prog_data);
+ wm, &brw->wm.base, brw->wm.base.prog_data);
}
}
--
2.7.4
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