[Mesa-dev] [PATCH] radeonsi: set VGT_GS_ONCHIP_CNTL on CIK and later

[Alex Deucher]

On Thu, Oct 27, 2016 at 9:40 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> On 26.10.2016 01:16, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> ---
>>  src/gallium/drivers/radeonsi/si_state.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_state.c
>> b/src/gallium/drivers/radeonsi/si_state.c
>> index 42689da..0633b64 100644
>> --- a/src/gallium/drivers/radeonsi/si_state.c
>> +++ b/src/gallium/drivers/radeonsi/si_state.c
>> @@ -3918,20 +3918,28 @@ static void si_init_config(struct si_context
>> *sctx)
>>         si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
>>         si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
>>         si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
>>         si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
>>
>>         si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
>>         si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
>>         si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
>>
>>         if (sctx->b.chip_class >= CIK) {
>> +               /* If this is 0, Bonaire can hang even if GS isn't being
>> used.
>> +                * Other chips are unaffected. These are suboptimal
>> values,
>> +                * but we don't use on-chip GS.
>> +                */
>> +               si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
>> +                              S_028A44_ES_VERTS_PER_SUBGRP(64) |
>> +                              S_028A44_GS_PRIMS_PER_SUBGRP(4));
>
>
> *sigh* Good find.
>
> Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

CC stable?

Alex