[Mesa-dev] [RFC 09/11] i965/compiler: Take an explicit shader_info parameter in compile_gs
Jason Ekstrand
jason at jlekstrand.net
Fri Oct 28 20:46:38 UTC 2016
---
src/intel/vulkan/anv_pipeline.c | 2 +-
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_gs.c | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 39 ++++++++++++-----------
4 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 4e7a725..9481e18 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -553,7 +553,7 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
unsigned code_size;
const unsigned *shader_code =
- brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
+ brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir->info, nir,
NULL, -1, &code_size, NULL);
if (shader_code == NULL) {
ralloc_free(mem_ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
index 00120c9..4fe9343 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -822,6 +822,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
+ shader_info *info,
const struct nir_shader *shader,
struct gl_shader_program *shader_prog,
int shader_time_index,
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 0f052d2..f2f54e8 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -160,7 +160,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
char *error_str;
const unsigned *program =
brw_compile_gs(brw->screen->compiler, brw, mem_ctx, key,
- &prog_data, gs->Program->nir, prog,
+ &prog_data, &gs->Program->info, gs->Program->nir, prog,
st_index, &program_size, &error_str);
if (program == NULL) {
ralloc_strcat(&prog->InfoLog, error_str);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 7671d32..3dcf509 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -590,6 +590,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
+ shader_info *info,
const nir_shader *src_shader,
struct gl_shader_program *shader_prog,
int shader_time_index,
@@ -615,10 +616,10 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* written by previous stages and shows up via payload magic.
*/
GLbitfield64 inputs_read =
- shader->info->inputs_read & ~VARYING_BIT_PRIMITIVE_ID;
+ info->inputs_read & ~VARYING_BIT_PRIMITIVE_ID;
brw_compute_vue_map(compiler->devinfo,
&c.input_vue_map, inputs_read,
- shader->info->separate_shader);
+ info->separate_shader);
shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
is_scalar);
@@ -627,15 +628,15 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
prog_data->include_primitive_id =
- (shader->info->inputs_read & VARYING_BIT_PRIMITIVE_ID) != 0;
+ (info->inputs_read & VARYING_BIT_PRIMITIVE_ID) != 0;
- prog_data->invocations = shader->info->gs.invocations;
+ prog_data->invocations = info->gs.invocations;
if (compiler->devinfo->gen >= 8)
prog_data->static_vertex_count = nir_gs_count_vertices(shader);
if (compiler->devinfo->gen >= 7) {
- if (shader->info->gs.output_primitive == GL_POINTS) {
+ if (info->gs.output_primitive == GL_POINTS) {
/* When the output type is points, the geometry shader may output data
* to multiple streams, and EndPrimitive() has no effect. So we
* configure the hardware to interpret the control data as stream ID.
@@ -660,20 +661,20 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* EndPrimitive().
*/
c.control_data_bits_per_vertex =
- shader->info->gs.uses_end_primitive ? 1 : 0;
+ info->gs.uses_end_primitive ? 1 : 0;
}
} else {
/* There are no control data bits in gen6. */
c.control_data_bits_per_vertex = 0;
/* If it is using transform feedback, enable it */
- if (shader->info->has_transform_feedback_varyings)
+ if (info->has_transform_feedback_varyings)
prog_data->gen6_xfb_enabled = true;
else
prog_data->gen6_xfb_enabled = false;
}
c.control_data_header_size_bits =
- shader->info->gs.vertices_out * c.control_data_bits_per_vertex;
+ info->gs.vertices_out * c.control_data_bits_per_vertex;
/* 1 HWORD = 32 bytes = 256 bits */
prog_data->control_data_header_size_hwords =
@@ -768,7 +769,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
unsigned output_size_bytes;
if (compiler->devinfo->gen >= 7) {
output_size_bytes =
- prog_data->output_vertex_size_hwords * 32 * shader->info->gs.vertices_out;
+ prog_data->output_vertex_size_hwords * 32 * info->gs.vertices_out;
output_size_bytes += 32 * prog_data->control_data_header_size_hwords;
} else {
output_size_bytes = prog_data->output_vertex_size_hwords * 32;
@@ -797,9 +798,9 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128;
prog_data->output_topology =
- get_hw_prim_for_gl_prim(shader->info->gs.output_primitive);
+ get_hw_prim_for_gl_prim(info->gs.output_primitive);
- prog_data->vertices_in = shader->info->gs.vertices_in;
+ prog_data->vertices_in = info->gs.vertices_in;
/* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
* need to program a URB read length of ceiling(num_slots / 2).
@@ -818,7 +819,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
if (is_scalar) {
fs_visitor v(compiler, log_data, mem_ctx, &c, prog_data, shader,
- shader->info, shader_time_index);
+ info, shader_time_index);
if (v.run_gs()) {
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
@@ -828,9 +829,9 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
false, MESA_SHADER_GEOMETRY);
if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
const char *label =
- shader->info->label ? shader->info->label : "unnamed";
+ info->label ? info->label : "unnamed";
char *name = ralloc_asprintf(mem_ctx, "%s geometry shader %s",
- label, shader->info->name);
+ label, info->name);
g.enable_debug(name);
}
g.generate_code(v.cfg, 8);
@@ -847,11 +848,11 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) {
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
- vec4_gs_visitor v(compiler, log_data, &c, prog_data, shader, shader->info,
+ vec4_gs_visitor v(compiler, log_data, &c, prog_data, shader, info,
mem_ctx, true /* no_spills */, shader_time_index);
if (v.run()) {
return brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
- shader, shader->info, &prog_data->base,
+ shader, info, &prog_data->base,
v.cfg, final_assembly_size);
}
}
@@ -890,11 +891,11 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
if (compiler->devinfo->gen >= 7)
gs = new vec4_gs_visitor(compiler, log_data, &c, prog_data,
- shader, shader->info, mem_ctx, false /* no_spills */,
+ shader, info, mem_ctx, false /* no_spills */,
shader_time_index);
else
gs = new gen6_gs_visitor(compiler, log_data, &c, prog_data, shader_prog,
- shader, shader->info, mem_ctx, false /* no_spills */,
+ shader, info, mem_ctx, false /* no_spills */,
shader_time_index);
if (!gs->run()) {
@@ -902,7 +903,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
*error_str = ralloc_strdup(mem_ctx, gs->fail_msg);
} else {
ret = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, shader,
- shader->info, &prog_data->base, gs->cfg,
+ info, &prog_data->base, gs->cfg,
final_assembly_size);
}
--
2.5.0.400.gff86faf
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