[Mesa-dev] [PATCH 08/10] gallium/radeon: make it clear that DRM 2.x.x fast clear constraint is CIK-only

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_texture.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 6c8d5a7..7ced41c 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2450,22 +2450,22 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 
 		/* shared textures can't use fast clear without an explicit flush,
 		 * because there is no way to communicate the clear color among
 		 * all clients
 		 */
 		if (tex->resource.is_shared &&
 		    !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
 			continue;
 
 		/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
-		if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
-		    rctx->chip_class >= CIK &&
+		if (rctx->chip_class == CIK &&
+		    tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
 		    rctx->screen->info.drm_major == 2 &&
 		    rctx->screen->info.drm_minor < 38) {
 			continue;
 		}
 
 		/* Fast clear is the most appropriate place to enable DCC for
 		 * displayable surfaces.
 		 */
 		if (rctx->chip_class >= VI &&
 		    !(rctx->screen->debug_flags & DBG_NO_DCC_FB)) {
-- 
2.7.4