[Mesa-dev] [PATCH 23/26] i965: Restructure fast clear eligibility decision

[Jason Ekstrand]

On Tue, Oct 11, 2016 at 12:26 PM, Topi Pohjolainen <
topi.pohjolainen at gmail.com> wrote:

> From: Ben Widawsky <ben at bwidawsk.net>
>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 51
> ++++++++++++++++++---------
>  1 file changed, 34 insertions(+), 17 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index f51392f..a41a654 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -224,33 +224,50 @@ intel_miptree_supports_non_msrt_fast_clear(struct
> brw_context *brw,
>        return false;
>     }
>
> +   /* Handle the hardware restrictions...
> +    *
> +    * All GENs have the following restriction: "MCS buffer for non-MSRT is
> +    * supported only for RT formats 32bpp, 64bpp, and 128bpp."
> +    *
> +    * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
> +    * Non-MultiSampler Render Target Restrictions) Support is for
> non-mip-mapped
> +    * and non-array surface types only.
> +    *
> +    * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
> +    * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
> +    * surfaces are supported with MCS buffer layout with these alignments
> in the
> +    * RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
> +    *
> +    * Skylake and above (docs are currently unpublished) are similar to
> BDW with
>

Heh... Old patch.  We should put in the real PRM citation.


> +    * looser restrictions.
> +    */
> +   const bool mip_mapped = mt->first_level != 0 || mt->last_level != 0;
> +   const bool arrayed = mt->physical_depth0 != 1;
> +
>     if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
>        return false;
> -   if (mt->first_level != 0 || mt->last_level != 0) {
> -      if (brw->gen >= 8) {
> +
> +   if (mip_mapped || arrayed) {
> +      /* Multisample surfaces with the CMS layout are not layered
> surfaces, yet
> +       * still have physical_depth0 > 1. Assert that we don't accidentally
> +       * reject a multisampled surface here. We should have rejected it
> earlier
> +       * by explicitly checking the sample count.
> +       */
> +      if (arrayed)
> +         assert(mt->num_samples <= 1);
> +
> +      if (mip_mapped && brw->gen >= 8) {
>           perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
>                      mt->logical_width0, mt->logical_height0,
> mt->last_level);
> +         return false;
>        }
>
> -      return false;
> -   }
> -
> -   /* Check for layered surfaces. */
> -   if (mt->physical_depth0 != 1) {
> -       /* Multisample surfaces with the CMS layout are not layered
> surfaces,
> -        * yet still have physical_depth0 > 1. Assert that we don't
> -        * accidentally reject a multisampled surface here. We should have
> -        * rejected it earlier by explicitly checking the sample count.
> -        */
> -      assert(mt->num_samples <= 1);
> -
> -      if (brw->gen >= 8) {
> +      if (arrayed && brw->gen >= 8) {
>           perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
>                      mt->logical_width0, mt->logical_height0,
>                      mt->physical_depth0);
> +         return false;
>        }
> -
> -      return false;
>     }
>
>     /* There's no point in using an MCS buffer if the surface isn't in a
> --
> 2.5.5
>
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