[Mesa-dev] [PATCH 20/20] gallium/radeon: remove VPORT_ZMIN/ZMAX from init config states
Nicolai Hähnle
nhaehnle at gmail.com
Thu Sep 1 15:13:32 UTC 2016
Patches 8-20:
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
On 29.08.2016 17:28, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> It's part of the viewport state now.
> ---
> src/gallium/drivers/r600/evergreen_state.c | 14 +-------------
> src/gallium/drivers/r600/r600_state.c | 6 ------
> src/gallium/drivers/radeonsi/si_state.c | 6 ------
> 3 files changed, 1 insertion(+), 25 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index 5ca5453..ed385ee 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -2323,21 +2323,21 @@ void cayman_init_common_regs(struct r600_command_buffer *cb,
> r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
> r600_store_value(cb, 0);
> r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
>
> r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
> }
>
> static void cayman_init_atom_start_cs(struct r600_context *rctx)
> {
> struct r600_command_buffer *cb = &rctx->start_cs_cmd;
> - int tmp, i;
> + int i;
>
> r600_init_command_buffer(cb, 338);
>
> /* This must be first. */
> r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
> r600_store_value(cb, 0x80000000);
> r600_store_value(cb, 0x80000000);
>
> /* We're setting config registers here. */
> r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
> @@ -2415,26 +2415,20 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
> r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
>
> r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
> r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
> r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
> r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
>
> r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
> r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
>
> - r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
> - for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
> - r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
> - r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
> - }
> -
> r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
> r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
>
> r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
> r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
> r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
>
> r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
> r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
> r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
> @@ -2825,26 +2819,20 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
> r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
>
> r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
>
> r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
>
> r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
> r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
> r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
>
> - r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
> - for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
> - r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
> - r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
> - }
> -
> r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
> r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
>
> r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
> r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
> r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
> r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
>
> r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
> r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
> diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
> index c8768e0..c55c532 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -2367,26 +2367,20 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
> r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
>
> r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
> r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
> r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
> r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
>
> r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
> r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
>
> - r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
> - for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
> - r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
> - r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
> - }
> -
> r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
> r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
>
> if (rctx->b.chip_class >= R700) {
> r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
> }
>
> r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
> r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
> r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 526f628..c765ea7 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3751,21 +3751,20 @@ si_write_harvested_raster_configs(struct si_context *sctx,
> }
>
> static void si_init_config(struct si_context *sctx)
> {
> struct si_screen *sscreen = sctx->screen;
> unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
> unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
> unsigned raster_config, raster_config_1;
> uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
> struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
> - int i;
>
> if (!pm4)
> return;
>
> si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
> si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
> si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
> si_pm4_cmd_end(pm4, false);
>
> si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
> @@ -3783,25 +3782,20 @@ static void si_init_config(struct si_context *sctx)
> si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
> if (sctx->b.chip_class < CIK)
> si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
> S_008A14_CLIP_VTX_REORDER_ENA(1));
>
> si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
> si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
>
> si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
>
> - for (i = 0; i < 16; i++) {
> - si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
> - si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
> - }
> -
> switch (sctx->screen->b.family) {
> case CHIP_TAHITI:
> case CHIP_PITCAIRN:
> raster_config = 0x2a00126a;
> raster_config_1 = 0x00000000;
> break;
> case CHIP_VERDE:
> raster_config = 0x0000124a;
> raster_config_1 = 0x00000000;
> break;
>
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