[Mesa-dev] [PATCH 18/57] i965/vec4: Take into account misalignment in regs_written() and regs_read().

[Francisco Jerez]

Unlike the FS counterpart of this commit this was likely not (yet) a
bug, but let's fix it already in preparation for implementing support
for sub-GRF offsets in the VEC4 back-end.
---
 src/mesa/drivers/dri/i965/brw_ir_vec4.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 2fd5441..9910d87 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -263,9 +263,10 @@ set_saturate(bool saturate, vec4_instruction *inst)
 inline unsigned
 regs_written(const vec4_instruction *inst)
 {
-   /* XXX - Take into account register-misaligned offsets correctly. */
+   /* XXX - Use reg_offset() as promised by the comment above. */
    assert(inst->dst.file != UNIFORM && inst->dst.file != IMM);
-   return DIV_ROUND_UP(inst->size_written, REG_SIZE);
+   return DIV_ROUND_UP(inst->dst.offset % REG_SIZE + inst->size_written,
+                       REG_SIZE);
 }
 
 /**
@@ -277,10 +278,11 @@ regs_written(const vec4_instruction *inst)
 inline unsigned
 regs_read(const vec4_instruction *inst, unsigned i)
 {
-   /* XXX - Take into account register-misaligned offsets correctly. */
+   /* XXX - Use reg_offset() as promised by the comment above. */
    const unsigned reg_size =
       inst->src[i].file == UNIFORM || inst->src[i].file == IMM ? 16 : REG_SIZE;
-   return DIV_ROUND_UP(inst->size_read(i), reg_size);
+   return DIV_ROUND_UP(inst->src[i].offset % reg_size + inst->size_read(i),
+                       reg_size);
 }
 
 } /* namespace brw */
-- 
2.9.0