[Mesa-dev] [PATCH 56/57] i965/vec4: Assert that ATTR regions are register-aligned.

[Francisco Jerez]

It might be useful to actually handle this once copy propagation
becomes smarter about register-misaligned offsets.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 470f814..58c8a8a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1620,6 +1620,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
 
          int grf = attribute_map[inst->src[i].nr +
                                  inst->src[i].offset / REG_SIZE];
+         assert(inst->src[i].offset % REG_SIZE == 0);
 
          /* All attributes used in the shader need to have been assigned a
           * hardware register by the caller
-- 
2.9.0